Transmitter Interface Design and Gain Calculation
For Tx-channel designs, both ZIF and superheterodyne architectures have similar interface characteristics, and both need dc coupling between the TxDAC® and the modulator. Most modulators’ IF input circuits should be biased by a dc voltage externally; the TxDAC output can provide dc bias for the modulator in a dc-coupled mode. Most high-speed DACs have current outputs, so an output resistor is needed to produce an output voltage for the modulator.
Figure 5 shows a superheterodyne or ZIF transmitter implemented with an AD9122 TxDAC, a low-pass filter, an ADL537x quadrature modulator, another RF filter, an ADF4350 synthesizer, an ADL5243 digitally controlled VGA, a power amplifier, and an AD562x DAC to control the power amplifier’s (PA) gate voltage.
Figure 5. Transmitter diagram.
For the AD9122, the full-scale output current can be set between 8.66 mA and 31.66 mA. For full-scale currents greater than 20 mA, the spurious-free dynamic range (SFDR) is decreased, but the output power and ACPR of the DAC decrease with lower full-scale current settings. A suitable compromise is a 0-mA to 20-mA current output consisting of a 20-mA ac current riding on a 10-mA dc level.
The input circuit of the ADL5372 needs a 0.5-V common-mode voltage, which is provided by a 10-mA dc current flowing through a 50-Ω resistor. The 0-mA to 20-mA ac current is shared by two 50-Ω resistors and a 100-Ω resistor. The ac voltage between the modulator inputs is thus 20 mA × ((50 × 2) || 100) = 1 V p-p. The filter between the TxDAC and the modulator removes unwanted frequency components. The input and output impedance of the filter is 100 Ω. The complete interface is shown in Figure 6.
Figure 6. DC coupled transmitter IF interface diagram and filter simulation result.
With a 50-Ω output, the voltage conversion gain of the ADL5372 is 0.2 dBm. With a 13-dB PAR modulator signal, the average power must be reduced by at least 15 dB for the Tx digital predistortion process. With a 1-V p-p single-tone input to the ADL5372, the average modulator output power is 7.1 dBm – 2.9 dBm = 4.2 dBm. If the 2.2-dBm insertion loss of the low-pass filter is considered, the peak output power is 4.2 dBm – 2.2 dBm = 2 dBm. In this state, an average output power of –10 dBm is presented at the output of the modulator.
With an 11-dBm average power signal, a PA-driver with 26-dBm P1dB is needed in the Tx signal chain. If a 2-dB insertion-loss RF filter is needed to suppress LO feedthrough and sideband output of the modulator, then the gain block and PA driver have to provide a total of 21-dB gain. The ADL5243 VGA with integrated gain block, digitally controlled attenuator, and PA driver is suggested for this application.
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Additional information can be found in the following references:
Circuit Note CN-0018
, Interfacing the ADL5372 I/Q Modulator to the AD9779A Dual-Channel, 1 GSPS High-Speed DAC.
Circuit Note CN-0134
, Broadband Low Error Vector Magnitude (EVM) Direct Conversion Transmitter.
Calvo, Carlos. “The differential-signal advantage for communications system design
.” EE Times RF & Microwave Designline.
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Mingming Zhao is a field applications engineer for Analog Devices, Inc. in Beijing, China. He has been with ADI since 2010 and is responsible for supporting RF and high-speed converter product applications. He has a master’s degree in Electromagnetic and Microwave Technology from the Chinese Academy of Sciences. He can be reached at firstname.lastname@example.org.