Design Article
Multichannel DDS enables efficient FSK/PSK modulation
David Brandon and Jeff Keip, Analog Devices, Inc.
5/14/2012 3:19 PM EDT
How to Implement
A DDS inherently switches frequency in a phase-continuous manner. This means that no instantaneous phase change occurs when the frequency tuning word changes. That is, the accumulator starts accumulating the new FTW from whatever phase position it was at when the new FTW was applied. Phase coherence, on the other hand, requires an instantaneous transition to the phase of the new frequency as if the new frequency had been present all along. Therefore, in order for a standard DDS to implement a phase-coherent FSK switch, the change from a mark frequency to a space frequency must occur when both frequencies have the same absolute phase.
To implement a zero-crossing switch in a phase-coherent manner, the DDS must make the frequency transition at 0 degrees (that is, when the accumulator overflows with zero excess). Therefore, we must determine the instants at which phase coherent zero-crossings occur. If the GRR of the mark and space FTWs are known, the smaller of the two GRRs (if different) will indicate the desired phase coherent zero-crossing point.
Three criteria are necessary for implementing a phase-coherent zero-crossing switch:
1. The ability to determine the smaller GRR of the mark and space FTWs associated with CH0 of Figure 2.
2. A second DDS channel (CH1 of Figure 2) synchronized to CH0 of Figure 2 and programmed with an FTW having all zeros except for the one bit corresponding to the smaller GRR.
3. The capability to use the rollover of the second channel to trigger a frequency change on CH0 of Figure 2.
Unfortunately, the latency between when a DDS accumulator hits zero and when that zero phase is represented at the output further complicates the solution. Fortunately, this latency is constant. The ideal solution necessitates that the auxiliary channel be phase adjusted to compensate for this latency. Both channels on the AD9958 have a phase-offset word that can be used to fix this problem.
The AD9958 two-channel DDS produced the results shown in Figure 4 through 8. Figure 4 and Figure 5 exhibit phase-continuous FSK switching versus zero-crossing FSK switching. Figure 5 shows both phase continuous switching and phase coherent switching. Figure 6 shows the results from a pseudorandom sequence (PRS) data stream that toggles between multiple frequencies.
Figure 4. Phase-continuous FSK transition.
Figure 5. Zero-crossing FSK transition.
Figure 6. Zero-crossing with multi-FSK transitions.
Figure 7 and Figure 8 exhibit phase-continuous BPSK switching versus zero-crossing BPSK switching.
Figure 7. Phase-continuous BPSK transition.
Figure 8. Zero-crossing BPSK transition.
About the Authors
David Brandon has supported DDS products since the first DDS released back in 1995. His career spans 28 years at ADI, with the last 11 years as an applications engineer in the Clock and Signal Synthesis Group. He has authored a number of application notes and a couple of magazine articles.
Jeff Keip has nearly 20 years of experience in the semiconductor industry; over 15 of those have been spent working on and with frequency synthesis products. For the past nine years, Jeff has had primary responsibility for the high-speed DDS product portfolio at ADI.
About the AD9958 Synthesizer
The AD9958 two-channel direct digital synthesizer (DDS) comes complete with two 10-bit, 500-MSPS current-output DACs, as shown in Figure 9. Both channels share a common system clock, providing inherent synchronization; additional packages can be used if more than two channels are required. The frequency, phase, and amplitude of each channel can be independently controlled, allowing them to provide correction for system-related mismatches. These parameters can be swept linearly; or 16 levels can be chosen for FSK, PSK, or ASK modulation. Output sine waves can be tuned with 32-bit frequency resolution, 14-bit phase resolution, and 10-bit amplitude resolution. Operating with a 1.8-V core supply, plus a 3.3-V I/O supply for logic compatibility, the AD9958 consumes 315 mW with all channels on, and 13 mW in power-down mode. Specified from –40°C to 85°C, it is available in a 56-lead LFCSP package and priced at $20.24 in 1000s.
Figure 9. AD9958 block diagram
References
1. Brandon, David. “Multichannel DDS Enables Phase-Coherent FSK Modulation,” Analog Dialog, Volume 44, November 2010. URL: http://www.analog.com/library/analogDialogue/archives/44-11/phase_coherent.html
2. More information on the AD9958
A DDS inherently switches frequency in a phase-continuous manner. This means that no instantaneous phase change occurs when the frequency tuning word changes. That is, the accumulator starts accumulating the new FTW from whatever phase position it was at when the new FTW was applied. Phase coherence, on the other hand, requires an instantaneous transition to the phase of the new frequency as if the new frequency had been present all along. Therefore, in order for a standard DDS to implement a phase-coherent FSK switch, the change from a mark frequency to a space frequency must occur when both frequencies have the same absolute phase.
To implement a zero-crossing switch in a phase-coherent manner, the DDS must make the frequency transition at 0 degrees (that is, when the accumulator overflows with zero excess). Therefore, we must determine the instants at which phase coherent zero-crossings occur. If the GRR of the mark and space FTWs are known, the smaller of the two GRRs (if different) will indicate the desired phase coherent zero-crossing point.
Three criteria are necessary for implementing a phase-coherent zero-crossing switch:
1. The ability to determine the smaller GRR of the mark and space FTWs associated with CH0 of Figure 2.
2. A second DDS channel (CH1 of Figure 2) synchronized to CH0 of Figure 2 and programmed with an FTW having all zeros except for the one bit corresponding to the smaller GRR.
3. The capability to use the rollover of the second channel to trigger a frequency change on CH0 of Figure 2.
Unfortunately, the latency between when a DDS accumulator hits zero and when that zero phase is represented at the output further complicates the solution. Fortunately, this latency is constant. The ideal solution necessitates that the auxiliary channel be phase adjusted to compensate for this latency. Both channels on the AD9958 have a phase-offset word that can be used to fix this problem.
The AD9958 two-channel DDS produced the results shown in Figure 4 through 8. Figure 4 and Figure 5 exhibit phase-continuous FSK switching versus zero-crossing FSK switching. Figure 5 shows both phase continuous switching and phase coherent switching. Figure 6 shows the results from a pseudorandom sequence (PRS) data stream that toggles between multiple frequencies.
Figure 4. Phase-continuous FSK transition.
Figure 5. Zero-crossing FSK transition.
Figure 6. Zero-crossing with multi-FSK transitions.
Figure 7 and Figure 8 exhibit phase-continuous BPSK switching versus zero-crossing BPSK switching.
Figure 7. Phase-continuous BPSK transition.
Figure 8. Zero-crossing BPSK transition.
About the Authors
David Brandon has supported DDS products since the first DDS released back in 1995. His career spans 28 years at ADI, with the last 11 years as an applications engineer in the Clock and Signal Synthesis Group. He has authored a number of application notes and a couple of magazine articles.
Jeff Keip has nearly 20 years of experience in the semiconductor industry; over 15 of those have been spent working on and with frequency synthesis products. For the past nine years, Jeff has had primary responsibility for the high-speed DDS product portfolio at ADI.
About the AD9958 Synthesizer
The AD9958 two-channel direct digital synthesizer (DDS) comes complete with two 10-bit, 500-MSPS current-output DACs, as shown in Figure 9. Both channels share a common system clock, providing inherent synchronization; additional packages can be used if more than two channels are required. The frequency, phase, and amplitude of each channel can be independently controlled, allowing them to provide correction for system-related mismatches. These parameters can be swept linearly; or 16 levels can be chosen for FSK, PSK, or ASK modulation. Output sine waves can be tuned with 32-bit frequency resolution, 14-bit phase resolution, and 10-bit amplitude resolution. Operating with a 1.8-V core supply, plus a 3.3-V I/O supply for logic compatibility, the AD9958 consumes 315 mW with all channels on, and 13 mW in power-down mode. Specified from –40°C to 85°C, it is available in a 56-lead LFCSP package and priced at $20.24 in 1000s.
Figure 9. AD9958 block diagram
References
1. Brandon, David. “Multichannel DDS Enables Phase-Coherent FSK Modulation,” Analog Dialog, Volume 44, November 2010. URL: http://www.analog.com/library/analogDialogue/archives/44-11/phase_coherent.html
2. More information on the AD9958
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kmeagher
5/16/2012 10:44 AM EDT
" the rightmost nonzero bit of either FTW is the 19th bit, so GRR = 1 GHz/219, or approximately 1907 Hz." Is there a mistake in the math, or is 1907 Hz something other than GRR?
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THurtado
5/16/2012 1:22 PM EDT
It's 2^19 not 219.
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