Tech primer: Understanding clock jitter and how to improve it

Challenges of designing low-jitter clocking
The total jitter is largely dominated by the noisiest contributor of the clock tree. Even though the additive jitter contribution of buffer1 is 76 fs_rms and of buffer2 is 55 fs_rms, due to rms addition the two buffers increase the total jitter by only 17 fs_rms. At first glance, this appears insignificant, but in a complicated, high-speed system where a single clock can be distributed to thousands of receivers through a large tree of fan-out buffers, their additive contribution to the jitter becomes significant.

The challenges of designing low-jitter clocking are compounded by the power consumption requirements typically present in high bandwidth applications. Because advanced boards use a variety of high speed ICs including framers, mappers, processors, and FPGAs, they usually have complex power supply requirements with heavy load transitions. In these systems, the power supply rail is never entirely clean. High current requirements force system designers to use switching power supplies that generate noise. Often, the noise is broadband, ranging from 100 kHz to several megahertz, placing the noise in the pass band of sensitive ICs that require a clean spectrum from 12 kHz to 20 MHz offsets. In many cases, the noise is also unpredictable with frequencies and amplitudes of ripple that vary as the load varies (see figure 2). For this reason, it may be challenging to design power supply decoupling networks that effectively filter noise across the entire band.



The top curve in figure 2 shows a device with minimal to no power supply noise rejection. It relies on heavy external filtering in order to provide a clean output signal. The lower curve shows a device with robust on-chip power supply noise rejection. The noise rejection is achieved by integrating low drop output regulators on-chip. When driving sensitive SoCs such as Gb PHYs that require 1-ps rms max jitter integrated from 12 kHz to 20 MHz, the clock device with inadequate on-chip VDD filtering meets the requirement on paper—but  fails in the actual system.

Because clock ICs are mixed signal circuits, there are sensitive nodes where noise can be injected into the clock signal. Any sub-circuit that is single ended and lacks common-mode rejection may be sensitive to noise, particularly those referenced to the VDD plane. It is best practice to isolate these nodes from VDD noise using on-chip low dropout regulators (LDOs). Indeed, the most robust ICs use LDOs to drive every circuit. The regulators must be broad-band and provide substantial power supply rejection, however. Otherwise, they are of little use in the presence of high power supply noise. Heavy external filtering will still be necessary. This is a non-trivial task and many IC design teams omit this while developing their products.

Clock vendors can no longer ignore the effects of power supply noise. With jitter budgets shrinking, it is now common practice for vendors to provide power supply noise rejection test results that allow system designers the ability to make proper tradeoffs prior to committing to a particular component. Choosing a weak IC without knowing that it should be carefully decoupled can lead to delays in product development. In worst case scenarios, it can make the entire system behave marginally or fail.

As the industry transitions to faster speeds and larger systems, picosecond clocks leave the high performance segment and transition to consumer markets. Datacom and telecom hardware designers are faced with new challenges and tradeoffs. Jitter performance has become the dominant consideration in selecting a PLL. Designers must work closely with knowledgeable vendors to select the appropriate synthesizers and distribution networks for their applications.

About the authors
Juan Conchas is marketing director for the Clock and Timing Business Unit and Aleksandr Borodulin is an Applications Engineer at Micrel.