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Single event effects (SEEs) in FPGAs, ASICs, and processors, part I: impact and analysis
Dagan White, Xilinx
12/14/2011 1:47 PM EST
Types of single-event effects
A number of events fall under the general category of SEEs (see figure 1). These events or errors can be divided into two broad categories: soft errors versus hard errors. Soft errors are those events that have no damaging effects and are cleared by normal device operation. Hard errors are events that generally result in lasting damage to the circuitry.
DRAM was the first technology for which terrestrial SEU became a concern, but these devices are now fairly robust. SRAM soft error rates (SERs) then became a concern, which has persisted because even though the per-bit SER has held steady despite the decreasing feature size, the total amount of SRAM bits per system/device has increased greatly. SRAM is used inside stand-alone memory devices as well as in FPGAs. Concern over FPGAs arises from their use of SRAM for user block memory as well as device-configuration memory. With the latest sub-90 nm technology nodes, concern over ASIC upset rates is rising.
SRAM-based FPGAs hold the device routing in a configuration memory, and they use block RAMs for user memory. Both of these memory structures, along with flip-flops, can be upset by radiation, although at different rates. User block RAM can be protected with error-correcting code (ECC) and parity schemes, as can external memory devices. FPGA configuration memory, however, cannot be directly protected in the same manner as block memory via ECC or parity checks. SEU mitigation techniques that monitor device configuration memories are recommended for FPGA designs. Ideally, a device should have built-in configuration memory error detection capabilities (using ECC) and SEU mitigation IP available to monitor and repair configuration memory. Other FPGA structures are upsettable as well but at an insignificant rate.
Note: The SRAM cells used for the configuration memory of FPGAs should be larger and more robust than the SRAM cells used for general-purpose memory, which are optimized for speed and cost. Moreover, configuration memory cells should be optimized for SEU resistance.
Next: SEE concerns in ASICs
A number of events fall under the general category of SEEs (see figure 1). These events or errors can be divided into two broad categories: soft errors versus hard errors. Soft errors are those events that have no damaging effects and are cleared by normal device operation. Hard errors are events that generally result in lasting damage to the circuitry.
Figure 1: Types of single event effects
Soft (recoverable) errors
Soft errors are upsets to the device operation and are self-correcting in time or are correctable by rewriting a memory element. The three subclasses of soft errors are:
- Single-event transients (SETs) result when a high-energy particle impacts a combinatorial path of a device and can induce a voltage/current spike. If the pulse-width of this spike is sufficient and at the right time, it can propagate through the circuit.
- Single-event upsets (SEUs) are the result of high-energy particles causing a change in the state of a memory element (SRAM, flash, flop, or latch). SEUs can be categorized as single-bit or multi-bit upsets (SBUs or MBUs). SBUs are by far the most common SEE seen in avionics applications.
- Single-event function interrupts (SEFIs) are disruptions to normal device operation that fall beyond a simple corruption of user data. These types of effects alter the functionality of the circuit and typically require reconfiguration/reset or power cycling for recovery.
Note: Failures-in-time (FIT) rates are commonly discussed in relation to SEUs, SETs, and SEFIs, but these are soft errors that affect the functionality and not permanent failures of the device.
Hard (non-recoverable) errorsASICs, FPGAs, and SEUs
Errors that cause lasting damage to the device are classified as hard errors. The three subclasses of hard errors are:
- Single-event latch-up (SEL) is a circuit latch-up induced by radiation. This latch-up can be either permanent or clearable with power cycling.
- Single-event burnout (SEB) is a short-circuiting caused when a high-energy ion impacts a transistor source, causing forward biasing. SEBs are typically a threat to power MOSFETs but are also seen in IGBTs, high-voltage diodes, and similar circuits.
- Single-event gate rupture (SEGR) is a plasma spike caused by a high-energy ion impact, resulting in rupture of the gate oxide insulation.
FPGAs can be protected from SEL, SEGR, and SEB caused by neutron radiation by careful fabrication and engineering processes, with little consideration of design, process, and technology variables. Likewise, space-grade parts can be rad-hard by design, and as such they can be made immune to latch-up from heavy ions. The process adds significant design challenge and device cost, however. Heavy ion radiation is not an issue inside of earth's atmosphere, so space-grade parts are not necessary for avionics applications.
DRAM was the first technology for which terrestrial SEU became a concern, but these devices are now fairly robust. SRAM soft error rates (SERs) then became a concern, which has persisted because even though the per-bit SER has held steady despite the decreasing feature size, the total amount of SRAM bits per system/device has increased greatly. SRAM is used inside stand-alone memory devices as well as in FPGAs. Concern over FPGAs arises from their use of SRAM for user block memory as well as device-configuration memory. With the latest sub-90 nm technology nodes, concern over ASIC upset rates is rising.
SRAM-based FPGAs hold the device routing in a configuration memory, and they use block RAMs for user memory. Both of these memory structures, along with flip-flops, can be upset by radiation, although at different rates. User block RAM can be protected with error-correcting code (ECC) and parity schemes, as can external memory devices. FPGA configuration memory, however, cannot be directly protected in the same manner as block memory via ECC or parity checks. SEU mitigation techniques that monitor device configuration memories are recommended for FPGA designs. Ideally, a device should have built-in configuration memory error detection capabilities (using ECC) and SEU mitigation IP available to monitor and repair configuration memory. Other FPGA structures are upsettable as well but at an insignificant rate.
Note: The SRAM cells used for the configuration memory of FPGAs should be larger and more robust than the SRAM cells used for general-purpose memory, which are optimized for speed and cost. Moreover, configuration memory cells should be optimized for SEU resistance.
Next: SEE concerns in ASICs
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