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Comparing FMCs with PMCs/XMCs for harsh environments (Part 1)
Jeremy Banks, Curtiss-Wright Controls Defense Solutions (CWCDS)
1/18/2012 2:52 PM EST
Understanding the FMC specification
The purpose of the FMC specification is to allow typically one FPGA on a host card to connect directly with the I/O devices on the mezzanine module, just as if the device were on the host board. Buses like PCI-X are redundant and would get in the way of the FPGA and its I/O devices. The tight connection allows the interface to be optimized and reduces demand for real estate, cost, and power, while boosting bandwidth and reducing latency.
An FMC is similar in height and width to a PMC, but around half the length. The reduced width, compared with PMC or XMC, allows up to three FMCs to be fitted to a 6U host. The FMC specification has a default stacking height of 10 mm, but permits a stacking height down to 8.5 mm for low-profile solutions.
The majority of FMC host/carriers use 3U/6UVPX, VXS and AMC formats but there are also PCI Express solutions such as the Xilinx ML605 Virtex-6 evaluation card7.
The FMC specification provides for a large number of differential connections—up to 80 pairs or 160 single-ended signals—to support high speed parallel interfaces between the FPGA and I/O devices. It also features as many as 10 pairs of serial connections suitable for multi-gigabit transceivers operating up to 10Gb/s. FMC modules and hosts support two connector options: a low pin count (LPC) 160-pin connector or high pin count (HPC) 400-pin connector. The majority of FMC solutions are likely to use the HPC variant.
Connectivity for FMC modules is unusual in that the standard defines only the upper limit of active connections, as opposed to the number of active connections. This means that host carriers need not provide the same number of FPGA signals as another host. This matters only in defining a given host’s ability to support certain FMC modules. Populating an HPC solution may require a large FPGA, so reduced pin-out offers cost sensitivity. This is something to be aware of, but the specification defines the signals to populate the LPC or HPC connector starting at a given position and to add to the connector in a given sequence, such that if two hosts provide x signals, they will use the same connector pins and be compatible.
Integration concerns
For power supply requirements, the FMC specification employs a useful trick, at least for the FMC: the host detects what the card’s power should be on its primary power rail and provides it. This is achieved through the host interrogating the FMC’s E2PROM, coupled with an adjustable power supply. The benefit to the FMC is a simplified power requirement, thereby freeing up valuable real estate for more I/O on the FMC.
Although it only occupies around half the printed wafer board area of an XMC, the FMC can sometimes achieve greater I/O functionality, most notably for rugged applications. If a solution requires a large FPGA and if the XMC module complies with the VITA 20 specification, there are restrictions on the location of the FPGA. These restrictions may in turn limit the area available for the I/O devices.
Consider a pair of designs using the same I/O devices for a rugged application, with one using an XMC format card and one using an FMC format card (see figure 3). The useful space in which to fit the I/O devices on an XMC is perhaps a quarter of the overall real estate of the card and not very efficient. Because the rugged XMC specification requires an area across the middle of the board to mate up with a host stiffening bar (which doubles as a primary thermal interface on conduction-cooled variants), a large FPGA, such as a 35 mm x 35 mm chip, invariably needs to be placed in the area of the circuit board closest to the front panel, just where the designer would want to fit the I/O devices.
In comparison, the FMC, though around half the size of the XMC, offers far greater real estate area for the I/O devices. In this example, the FMC is able to support two ADCs for two 3 GS/s channels, compared to the single channel of the XMC. Of course, an XMC using a smaller FPGA or not restricted by the rugged XMC specification may not be affected to such an extent, provided it still has a sufficient number of I/O connections to the devices. An FMC may be smaller, but it may still be able to support greater functionality than its larger XMC equivalent.
Next: Thermal management
The purpose of the FMC specification is to allow typically one FPGA on a host card to connect directly with the I/O devices on the mezzanine module, just as if the device were on the host board. Buses like PCI-X are redundant and would get in the way of the FPGA and its I/O devices. The tight connection allows the interface to be optimized and reduces demand for real estate, cost, and power, while boosting bandwidth and reducing latency.
An FMC is similar in height and width to a PMC, but around half the length. The reduced width, compared with PMC or XMC, allows up to three FMCs to be fitted to a 6U host. The FMC specification has a default stacking height of 10 mm, but permits a stacking height down to 8.5 mm for low-profile solutions.
The majority of FMC host/carriers use 3U/6UVPX, VXS and AMC formats but there are also PCI Express solutions such as the Xilinx ML605 Virtex-6 evaluation card7.
The FMC specification provides for a large number of differential connections—up to 80 pairs or 160 single-ended signals—to support high speed parallel interfaces between the FPGA and I/O devices. It also features as many as 10 pairs of serial connections suitable for multi-gigabit transceivers operating up to 10Gb/s. FMC modules and hosts support two connector options: a low pin count (LPC) 160-pin connector or high pin count (HPC) 400-pin connector. The majority of FMC solutions are likely to use the HPC variant.
Connectivity for FMC modules is unusual in that the standard defines only the upper limit of active connections, as opposed to the number of active connections. This means that host carriers need not provide the same number of FPGA signals as another host. This matters only in defining a given host’s ability to support certain FMC modules. Populating an HPC solution may require a large FPGA, so reduced pin-out offers cost sensitivity. This is something to be aware of, but the specification defines the signals to populate the LPC or HPC connector starting at a given position and to add to the connector in a given sequence, such that if two hosts provide x signals, they will use the same connector pins and be compatible.
Integration concerns
For power supply requirements, the FMC specification employs a useful trick, at least for the FMC: the host detects what the card’s power should be on its primary power rail and provides it. This is achieved through the host interrogating the FMC’s E2PROM, coupled with an adjustable power supply. The benefit to the FMC is a simplified power requirement, thereby freeing up valuable real estate for more I/O on the FMC.
Although it only occupies around half the printed wafer board area of an XMC, the FMC can sometimes achieve greater I/O functionality, most notably for rugged applications. If a solution requires a large FPGA and if the XMC module complies with the VITA 20 specification, there are restrictions on the location of the FPGA. These restrictions may in turn limit the area available for the I/O devices.
Consider a pair of designs using the same I/O devices for a rugged application, with one using an XMC format card and one using an FMC format card (see figure 3). The useful space in which to fit the I/O devices on an XMC is perhaps a quarter of the overall real estate of the card and not very efficient. Because the rugged XMC specification requires an area across the middle of the board to mate up with a host stiffening bar (which doubles as a primary thermal interface on conduction-cooled variants), a large FPGA, such as a 35 mm x 35 mm chip, invariably needs to be placed in the area of the circuit board closest to the front panel, just where the designer would want to fit the I/O devices.
Figure 3: For large FPGAs, FMCs present fewer space constraints and ruggedized XMCs.
In comparison, the FMC, though around half the size of the XMC, offers far greater real estate area for the I/O devices. In this example, the FMC is able to support two ADCs for two 3 GS/s channels, compared to the single channel of the XMC. Of course, an XMC using a smaller FPGA or not restricted by the rugged XMC specification may not be affected to such an extent, provided it still has a sufficient number of I/O connections to the devices. An FMC may be smaller, but it may still be able to support greater functionality than its larger XMC equivalent.
Next: Thermal management
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