Cooling rugged FPGA-based XMC cards can present a significant challenge because such boards can easily exceed 20 W power dissipation. Typical rugged air-cooled specifications for such cards define upper air-inlet temperatures of 70°C and conduction-cooled cold walls of 85°C. Making a mezzanine work within this environment with much lower power levels is already difficult. To compound this, XMC hosts often have two XMC sites.
Consider the size and orientation of an XMC. When plugged onto a 3U host card such as 3U VPX, an XMC covers the majority of host’s real estate which means, if there are any hot devices on the host, they are under the XMC. This is not ideal and can seriously affect cooling. The XMC mezzanine’s devices face down onto the host, not to the outside, placing the heat generating components opposite those on the host and compounding the cooling problem further. To cool the XMC, air needs to be squeezed between the host and mezzanine, which can be a very small cross section, thus limiting the volume of air available to cool the assembly. Conduction cooling is less difficult but having all the heat generators in one plane is still a problem as there may be hot spots. A 6U solution is not really any better; some of the host’s real estate is not covered by mezzanines, but the thermal paths to either the cooling air inlet or cold-wall interface are longer.
Cooling is another advantage for FMC based designs. An FMC, being smaller than an XMC, ensures that a larger amount of space on the host carrier is not covered by the mezzanine itself. Appropriate FMC host design allows for suitable heat sinks to be implemented in the areas not restricted by mezzanine placement. Superior cooling with either greater air-flow or greater heat-sink cross-sectional areas may be the factor that determines whether the solution is viable. In addition, as the FMC has no FPGA, only I/O devices, the FMC will be easier to cool as well—especially if the devices are not above a host’s thermal hot spot (see figure 4). The FMC specification limits the power dissipation of a single width module to 10W.
Figure 4: 6U VPX FMC host with two FMC sites (and 4x FPGAs)
In part two of this article, we will discuss how to choose the appropriate solution, focusing on the benefits and pitfalls of the technology.
1. IEEE 1386.1-2001 Standard Physical and Environmental Layers for PCI Mezzanine Cards
2. ANSI/VITA 39-2003: American National Standard for PCI-X Auxiliary Standard for PMCs and Processor PMCs.
3. ANSI/VITA 20 (R2005): American National Standard for Conduction Cooled PMC
4. ANSI/VITA 42.0-2008: STANDARD FOR VITA 42.0 XMC
5. ANSI/VITA 42.3-2006: American National Standard for XMC PCI Express Protocol Layer Standard
6. ANSI/VITA 57.1:-2008: American National Standard for FPGA Mezzanine Card (FMC) Standard
7. Xilinx ML605 Virtex-6 evaluation card: www.xilinx.com
Using FPGAs in mission-critical systems
Understanding and mitigating tin whiskers
High-performance FPGAs take flight in microsatellites
Xilinx FPGAs beam up next-gen radio astronomy
Xilinx rad-hard FPGA reaches for the stars
When perfect is good enough
Single event effects (SEEs) in FPGAs ASICs and processors
Transfer from FPGAs for prototype to ASICs for production
Design security yields secure FPGAs for mil/aero applications
About the author
Banks is the Sensor and I/O Processing Product Marketing Manager for
Curtiss-Wright Controls Defense Solutions. His career spans more than 25
years in embedded computing with the majority being within the defense
sector. During this time he has held a wide range of positions including
design engineering within hardware, software, and systems development;
marketing manager; and product management with single board computers,
DSP, FPGA, high speed I/O, and graphics portfolios. Banks holds a
bachelor of science degree in electronic and electrical engineering.
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