Key benefits of FMC (continued)
An FMC supports up to 80 differential signals, making it easy to conceive of parallel interfaces providing data throughputs in excess of 10 GB/s and largely limited only by the capabilities of the host FPGA. Although 80 differential signals represent significant connectivity, that connectivity is still finite. A monolithic design, not using a mezzanine, could provide more than 80 FPGA pairs to connect to the devices on the FMC.
The practicality of FMCs is determined by the host FPGA and I/O devices. Consider, for example a 3.6-GS/s 12-bit ADC, which exists today and might use 1:4 multiplexer to allow it to be interfaced to an FPGA. Such a device would require 48 low-voltage differential-signaling (LVDS) pairs, probably clocked at 450-MHz DDR. This would use more than half of the FMC’s connectivity for parallel connections for the data path alone, on top of which control signals would be needed. In this example only a single ADC device could be implemented on an FMC even though there may be sufficient space and power budget to fit on a second part; however, by comparison, the performance bandwidth for FMCs over XMCs is considerable.
Front panel I/O
FMC is a front-panel only format, unlike XMC and PMC which define user I/O signals that might be routed to a backplane for convenience. This is rarely used for analog signals where noise might be introduced through such routing, however. Mechanically, the FMC front panel width is slightly narrower than its XMC counterpart, leaving less room for connectors.
By its very definition, FMC requires an FPGA. This means the FMC will never achieve the universal appeal of PMC or XMC, but for applications that require the levels of performance provided by an FPGA, this is of minor consideration. Today, there are relative few FMCs and FMC host carriers, where PMC and XMC have built up an extensive portfolio number in the hundreds or even thousands with proven track records.
By definition, software and HDL for FMCs is defined by the host, and because the FMC is controlled by an FPGA, there is no real concept of a driver. So although FMCs from different third parties will fit together electronically and mechanically, there will be differences in the host’s environment, leading to incompatibility. Within the FPGA world, however, electrical and mechanical compatibility are of primary performance. HDL is frequently user specific and often not an issue.
The FMC format is gaining momentum. Already, more than fifteen vendors provide FMC modules, host or complete combinations. The majority of FMC solutions on the market today consist of high-speed analog input or output with good coverage of channel density, resolution, and ruggedization levels. This is not surprising because this is an area that requires raw bandwidth and FPGA processing. In addition, nearly hundred products no cover functionality such as tuners, digital I/O, fiber-optic, 10-gigabit Ethernet, and even FPGA co-processors. There are even products supporting system busses such as defined by MIL-STD-1553. Analog input products include solutions up to 250 MS/s 16-bit for high resolution, and 5 GS/s (10-bit) for high-speed capability.
Although FMC is now a published standard, there are some parallel specifications in development within the VME Industrial Trade Association (VITA). These deal with abstractions to simplify integration into systems such as FPGA driver concepts. When ready, these additional standards will strengthen some of the perceived weakness with FMC.
The choice of which mezzanine format is best for rugged embedded computing solutions ultimately comes down to factors like application details, perception of risk, development timeline, and personal preference. The primary criterion for choosing the most suitable mezzanine card for a given application is how it compares with a monolithic board (i.e. a single PWB with all functionality onboard). A monolithic card usually provides the best technical solution because it does not have the restrictions imposed by segmenting the design, such as number of connector I/O pins to the mezzanine. The question is whether it is most practical for a particular situation.
The FMC format is ready now as an electro-mechanical solution that serves a wide range of applications. The format does not really compete with PMC or XMC format so much as compliment them, particularly for high-bandwidth, low-latency applications. Indeed, FMCs promise to do for FPGA-based solutions what PMCs and XMCs did for embedded CPU-based systems.
1. IEEE 1386.1-2001 Standard Physical and Environmental Layers for PCI Mezzanine Cards
2. ANSI/VITA 42.0-2008: STANDARD FOR VITA 42.0 XMC
3. ANSI/VITA 39-2003: American National Standard for PCI-X Auxiliary Standard for PMCs and Processor PMCs.
4. ANSI/VITA 42.3-2006: American National Standard for XMC PCI Express Protocol Layer Standard
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About the author
Jeremy Banks is the Sensor and I/O Processing Product Marketing Manager for Curtiss-Wright Controls Defense Solutions. His career spans more than 25 years in embedded computing with the majority being within the defense sector. During this time he has held a wide range of positions including design engineering within hardware, software, and systems development; marketing manager; and product management with single board computers, DSP, FPGA, high speed I/O, and graphics portfolios. Banks holds a bachelor of science degree in electronic and electrical engineering.
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