The space industry has an increasing demand for advanced power management products that can survive harsh radiation environments and still provide “commercial-like” high performance capability. The Low Dropout Regulator (LDO) is often the device of choice when the load requirements are under 2Amps or when an easy to implement solution is desired. High sensitivity RF amplifier applications also dictate the use of LDOs over a switching regulator due to output noise performance capabilities. A switching regulator is a great fit when stepping down to a low voltage or when the current requirement exceeds 2A, necessitating a more efficient solution. With the adoption of next generation core processing solutions for satellite applications, such as FPGAs, the total power requirements and regulation tolerances are challenging designers to look beyond what is available today. For example, load current requirements are going up as core voltages are going down and voltage tolerances are being reduced from +/-10 percent to +/-5 percent in some cases. A power supply to meet this +/-5 percent tolerance -- with an output voltage accuracy over static and dynamic operation, temperature range, load transient response and single event transient performance – requires a next generation solution. For example, the Virtex V FPGA uses a core voltage of 1.0V +/-5 percent and an auxiliary supply voltage of 2.5V +/-5 percent.
Figure 1: A typical power system arrangement for an FPGA
The tight regulation specification required by FPGAs requires that the tolerances of the band gap reference of a switching regulator be accurate over the entire input and output operating voltage. Using a proportional to absolute temperature (PTAT) band gap and on-chip trimming can achieve this goal in monolithic power devices. The overall tolerance of the regulator is based on the device band gap accuracy, external setting resistor tolerances, and the effects of operating over the desired temperature range. If the initial accuracy of the device is fixed, for example +/-1.5 percent over temperature, the tolerance of the external resistors will be additive to this error term. For example, using +/-1 percent external resistors, will set the output voltage set point divider tolerance at +/-2.0 percent. Both of these add up to a total regulation error of +/-3.5 percent worst case. The core voltage of FPGAs & microprocessors now require the power regulator to regulate down to a typical output voltage of 1V +/-5 percent while including factors such as SET, load transient, line and load variation.
The satellite power system environment has to adapt itself to ever increasing clock rates, thereby demanding more power along with rapidly changing loads. This requires that the regulator have a good transient response, with a typical dI/dt of 10A/µs for a 0-percent to 100-percent load step. During these step load conditions, a maximum output voltage excursion +/-5 percent is desirable. Exceeding any of the FPGA maximum supply voltage limits during the load step can result in immediate or latent damage to the expensive FPGA, affecting system reliability. LDOs are the device of choice for loads of up to 2A, and integrated MOSFET switching regulators can be used for loads in the range of 2A to 12A. These devices have large energy storage capacitors on the output pin which impose a huge burden on the power bus during the power up cycle, causing bus load currents to increase momentarily by as much as an order magnitude. The use of the programmable soft start function available in these next generation devices will help keep the startup load current within a predetermined limit and avoid over designing of the power bus. The ability to build an intelligent power solution that can be controlled / sequenced from a microprocessor sub-system is desirable too. This is achieved by the enable and power good (PGOOD) functions. The enable function also serves the purpose of putting the regulator into a low quiescent power state. A programmable over current limit helps limit the energy dumped into a short-circuited load. Also, with switching frequency capability up to 1MHz, the external inductor and capacitors can be reduced in size, saving valuable board space. All of the above comes with minimal to no additional external components, unlike a discrete solution, which again minimizes the power solutions footprint and increases overall system reliability.
LDO designs commonly use a PMOS device as a pass element, which enables operation at a minimum input voltage of 2.2V typical and at lower quiescent ground current as a result of simpler drive circuits. Additionally, LDO devices provide very low ON resistance and dropout voltage. Typical dropout voltages seen with a device such as the ISL75051SRH are 65mV at 1A load current and 225mV at 3A. The low dropout and ground current help to reduce power consumption in satellite power systems, lower the temperature rise of the regulator, and result in cooler system operation.
Single event effects (SEE) include a range of destructive and nondestructive effects in the energetic proton and heavy ion environments commonly encountered in space. Destructive effects include single event burnout (SEB), in which the device suffers permanent damage. In single event latch up (SEL), parasitic PNPN structures internal to the chip are triggered and the device will enter a latch up condition causing noticeably higher supply current. If the SEL condition can be reset by recycling the power source, returning the supply current to normal, it is called a soft latch. Single event transient (SET) is a nondestructive (soft) error, which results in a short duration increase or decrease in the device’s output voltage. The magnitude of the SET pulse is an important parameter, as exceeding +/-5 percent power supply voltage tolerance of an FPGA can result in immediate destructive damage to the device, and SET performance is a major consideration in power management applications.