Design Article
Saving size, weight in avionics, military or space power distribution systems
5/11/2012 11:38 AM EDT
III. Load requirements
The POL-based distributed architecture allows the isolation boundary to be local to the input of the system board and the POL converters to be placed very close to their loads. Today’s high performance DSPs and FPGAs power specifications require very tight regulation on a low voltage, high current bus even during transients.
This regulation cannot be achieved unless the converter is placed very close to the load, where it can minimize impedance between the source and load. Placing the POL right next to the load allows this extremely tight regulation during load current transients. Because VPT POLs are very light, small, and efficient, one can place the converters at any required location on the system board without requiring large heatsinks and reinforcing structures.
If the load ripple voltage requirements are tighter than what is specified in the POL converter datasheet, then low ESR capacitors, placed between the converter output and the load, can reduce the ripple to the required levels. Bulk capacitance can also be placed at the input of the load to increase regulation performance during fast current transients. The VPT POL converters are all rated to operate with up to 5000 µF of external capacitance.
Many FPGAs require multiple voltages, such as one voltage to power the logic blocks and one or more voltages for the input/output sections. Often there are very strict requirements on the sequencing and rise and fall rate of the different voltages with respect to each other. Many POL converters have the functionality to meet these requirements. In the VPT POL converters, the track pin enables a great deal of flexibility for controlling the sequence of startup as well as the rate of rise and fall of multiple converters. Proper programming of the track pin allows coincident as well as ratio-metric rise and fall times between two or more POL converters. Figure 3 shows an example where an external signal is used to control the startup delay as well as the rise and fall times of two POL converters.
Another common requirement in multiple voltage power distribution systems is that one or more of the outputs must start into a pre-biased condition. Applying a voltage to a converter output (especially a synchronous rectified output converter) before it begins startup can cause many different problems [1]. The VPT POL converters are designed to monotonically start into a pre-biased output without overshoot, oscillations or reverse current. The only limitation is that the pre-bias voltage level is below the programmed output voltage setpoint of the POL converter.
A key to increasing power system efficiency is sizing the converters for the expected load current range for each load. DC-DC converters have a range of load current where the efficiency is greatest, typically from around 20 percent to 80 percent of full load, so the converter should be chosen such that the load current is in this range for the majority of the operational time. The VPT POL converter family offers a wide range of full load current levels (3A, 5A, 10A and 20A) that make it easy to optimize the power system efficiency.
Next: IV. System requirements
The POL-based distributed architecture allows the isolation boundary to be local to the input of the system board and the POL converters to be placed very close to their loads. Today’s high performance DSPs and FPGAs power specifications require very tight regulation on a low voltage, high current bus even during transients.
This regulation cannot be achieved unless the converter is placed very close to the load, where it can minimize impedance between the source and load. Placing the POL right next to the load allows this extremely tight regulation during load current transients. Because VPT POLs are very light, small, and efficient, one can place the converters at any required location on the system board without requiring large heatsinks and reinforcing structures.
If the load ripple voltage requirements are tighter than what is specified in the POL converter datasheet, then low ESR capacitors, placed between the converter output and the load, can reduce the ripple to the required levels. Bulk capacitance can also be placed at the input of the load to increase regulation performance during fast current transients. The VPT POL converters are all rated to operate with up to 5000 µF of external capacitance.
Many FPGAs require multiple voltages, such as one voltage to power the logic blocks and one or more voltages for the input/output sections. Often there are very strict requirements on the sequencing and rise and fall rate of the different voltages with respect to each other. Many POL converters have the functionality to meet these requirements. In the VPT POL converters, the track pin enables a great deal of flexibility for controlling the sequence of startup as well as the rate of rise and fall of multiple converters. Proper programming of the track pin allows coincident as well as ratio-metric rise and fall times between two or more POL converters. Figure 3 shows an example where an external signal is used to control the startup delay as well as the rise and fall times of two POL converters.
Figure 3: Track control connection and waveforms
Another common requirement in multiple voltage power distribution systems is that one or more of the outputs must start into a pre-biased condition. Applying a voltage to a converter output (especially a synchronous rectified output converter) before it begins startup can cause many different problems [1]. The VPT POL converters are designed to monotonically start into a pre-biased output without overshoot, oscillations or reverse current. The only limitation is that the pre-bias voltage level is below the programmed output voltage setpoint of the POL converter.
A key to increasing power system efficiency is sizing the converters for the expected load current range for each load. DC-DC converters have a range of load current where the efficiency is greatest, typically from around 20 percent to 80 percent of full load, so the converter should be chosen such that the load current is in this range for the majority of the operational time. The VPT POL converter family offers a wide range of full load current levels (3A, 5A, 10A and 20A) that make it easy to optimize the power system efficiency.
Next: IV. System requirements
|
|
|
|
|
Navigate to related information