Design Article
FPGA testing for DO-254 compliance
Louie De Luna, Aldec DO-254 program manager
5/22/2012 4:10 AM EDT
FPGA level in-target testing
The proposed methodology is based on a bit-accurate in-hardware verification platform that is able to verify FPGA pin level requirements from RTL to the target device at-speed.
The solution’s name is DO-254/CTS (Compliance Tool Set), a certifiable at-speed FPGA level in-hardware verification environment for DALs A/B complex designs, and is dedicated to address the stringent guidelines of DO-254 Section 6 Verification Process. DO-254/CTS consists of a fully customized hardware and software package designed to replay RTL simulation during in-hardware verification reusing the testbench as test vectors. It provides a single and automated environment to test all FPGA level requirements with full visibility and controllability at the FPGA pin level.
Automatic test vectors generation
For RTL simulation, testbenches are created to contain test vectors that verify the requirements. Reusing the same data will save tremendous time required for creation of the test vectors for in-hardware verification. The generation of test vectors based on the testbenches can be accomplished by adding a special simulator plug-in which enables storing the sequences of stimulators and events during RTL simulation. Additionally, the plug-in automatically generates test vectors from many different testbenches. The key benefits derived from using RTL simulation data for in-hardware verification include:
• All testbenches have been written
• Testbenches contain the requirements
• Requirements have been verified
• Code coverage has been reported
The flow of test vectors generation is displayed in Figure 2 below. The process generates two sets of vectors: Golden Vectors and Input Vectors. The Golden Vectors are the RTL simulation results which will be the reference for results comparison. The Input Vectors are the test vectors generated based on the testbench which will be used for in-hardware verification.
Figure 2: Test Vectors Generation Process
The proposed methodology is based on a bit-accurate in-hardware verification platform that is able to verify FPGA pin level requirements from RTL to the target device at-speed.
The solution’s name is DO-254/CTS (Compliance Tool Set), a certifiable at-speed FPGA level in-hardware verification environment for DALs A/B complex designs, and is dedicated to address the stringent guidelines of DO-254 Section 6 Verification Process. DO-254/CTS consists of a fully customized hardware and software package designed to replay RTL simulation during in-hardware verification reusing the testbench as test vectors. It provides a single and automated environment to test all FPGA level requirements with full visibility and controllability at the FPGA pin level.
Automatic test vectors generation
For RTL simulation, testbenches are created to contain test vectors that verify the requirements. Reusing the same data will save tremendous time required for creation of the test vectors for in-hardware verification. The generation of test vectors based on the testbenches can be accomplished by adding a special simulator plug-in which enables storing the sequences of stimulators and events during RTL simulation. Additionally, the plug-in automatically generates test vectors from many different testbenches. The key benefits derived from using RTL simulation data for in-hardware verification include:
• All testbenches have been written
• Testbenches contain the requirements
• Requirements have been verified
• Code coverage has been reported
The flow of test vectors generation is displayed in Figure 2 below. The process generates two sets of vectors: Golden Vectors and Input Vectors. The Golden Vectors are the RTL simulation results which will be the reference for results comparison. The Input Vectors are the test vectors generated based on the testbench which will be used for in-hardware verification.
Figure 2: Test Vectors Generation Process
The Test Vectors Generation Process offers several advantages:
• Time savings on test vectors development – automated process, no need to write new tests; a script- driven process generates vectors for all applicable testbenches.
• The RTL golden vectors provided by RTL simulation are treated as a reference for comparison with in-hardware verification results.
• Test vectors for in-hardware verification – if recorded in a waveform format, are used for additional review and analysis before and after in-hardware verification.
• Time savings on test vectors development – automated process, no need to write new tests; a script- driven process generates vectors for all applicable testbenches.
• The RTL golden vectors provided by RTL simulation are treated as a reference for comparison with in-hardware verification results.
• Test vectors for in-hardware verification – if recorded in a waveform format, are used for additional review and analysis before and after in-hardware verification.
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