Design Article
FPGA testing for DO-254 compliance
Louie De Luna, Aldec DO-254 program manager
5/22/2012 4:10 AM EDT
In-hardware verification process
Since the problem of test vectors creation has been resolved by automated test vectors generation, the next tasks now are to:
• Use the test vectors for at-speed in-hardware verification
• Document the results
• Trace the results to RTL simulations, ensure the RTL simulation and in-hardware verification results match
• Shorten the time spent on these activities.
Figure 3 shows the in-hardware verification process. The Input Vectors are uploaded from the workstation to mother board via PCIe interface. The Input Vectors are then processed and stored in a 2GB DDRII on-board memory (expandable) of the mother board. Once all of the vectors are stored, then real clocks will be released to start the at-speed in-hardware verification of the FPGA under test in the daughter board. The testing process is automated by a specialized application capable of reading and applying the Input Vectors file during in-hardware verification. This application controls the verification process by feeding the Input Vectors to FPGA pins at full speed using real clocks.
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Key characteristics of at-speed in-hardware verification:
• Input Vectors derived from RTL testbenches have known test coverage
• Input Vectors drive target device at-speed, which produces Output Vectors
• Golden Vectors in a waveform format allow fast analysis and documenting results
• Provides a script-driven verification environment for any test scenarios.
Since the problem of test vectors creation has been resolved by automated test vectors generation, the next tasks now are to:
• Use the test vectors for at-speed in-hardware verification
• Document the results
• Trace the results to RTL simulations, ensure the RTL simulation and in-hardware verification results match
• Shorten the time spent on these activities.
Figure 3 shows the in-hardware verification process. The Input Vectors are uploaded from the workstation to mother board via PCIe interface. The Input Vectors are then processed and stored in a 2GB DDRII on-board memory (expandable) of the mother board. Once all of the vectors are stored, then real clocks will be released to start the at-speed in-hardware verification of the FPGA under test in the daughter board. The testing process is automated by a specialized application capable of reading and applying the Input Vectors file during in-hardware verification. This application controls the verification process by feeding the Input Vectors to FPGA pins at full speed using real clocks.
The results obtained during in-hardware verification are sampled at full speed, and recorded in a waveform file called Output Vectors. Another specialized application automatically compares the in-hardware verification results (Output Vectors) with the RTL simulation results (Golden Vectors). Further investigation of any discrepancies can easily be done by using the waveform comparison feature of the RTL simulator.
.Figure 3. In-hardware verification process
Key characteristics of at-speed in-hardware verification:
• Input Vectors derived from RTL testbenches have known test coverage
• Input Vectors drive target device at-speed, which produces Output Vectors
• Golden Vectors in a waveform format allow fast analysis and documenting results
• Provides a script-driven verification environment for any test scenarios.
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