ENHANCED OPTIONS FOR VOLTAGE SCALING
Xilinx 7 series FPGAs offers significant voltage-scaling options.
The 7 series FPGAs offer an extended (E) temperature range (0–100°C) option for both -3 and -2L devices. Due to the headroom in the 28 HPL process, the -2LE devices can operate at 1 or 0.9 volt. These devices are referred to as -2L (1.0V) and -2L (0.9V). The -2L devices operating at 1.0V have the same speed-grade performance as the -2I and -2C devices, but with much lower static power. The -2L devices operating at 0.9V have performance similar to the -1I and -1C devices, but with even lower static and lower dynamic power.
At 0.9V, the voltage drop alone in these devices offers a static power reduction of around 30 percent. The voltage drop would also reduce performance, but Xilinx screens these -2L (0.9V) devices for speed and a tighter leakage specification. This screening method yields a 55 percent reduction in power at worst-case process compared with the standard-speed-grade devices.
By choosing a -2L family device, you can obtain additional power savings on dynamic power. Because dynamic power is proportional to VCCINT2, a 10 percent reduction in VCCINT will provide a 20 percent reduction of power.
POWER ESTIMATION TOOLS
There is an extensive choice of tools available in the market today to help designers evaluate the thermal and supply requirements of an FPGA design throughout the development cycle. Figure 3
shows the Xilinx tools available at each stage of the FPGA development cycle.
Figure 3 – Xilinx offers power estimation and analysis tools for every stage of the design cycle.
At the outset of the design cycle, the XPower Estimator (XPE) spreadsheet provides an early estimation of power consumption even before the predesign and preimplementation phases of a project. XPE assists with architecture evaluation and device selection and helps in selecting the appropriate power supply and thermal-management components that may be required for the application.
The PlanAhead™ software estimates the design power distribution at the RTL level. Designers can specify the device operating environment, the I/O properties and the default activity rates for the design using constraints or by using the GUI. The PlanAhead software then reads the HDL code to estimate the design resources needed and reports the estimated power from a statistical analysis of the activity of each resource. With its access to more-detailed information about the design intent, the RTL power estimator should be more accurate than the XPower Estimator spreadsheet and less accurate than the post-place-and-route analysis done with the XPower Analyzer.
XPower Analyzer (XPA) is a tool dedicated to the power analysis of placed-and-routed designs. It provides a comprehensive GUI that allows a detailed analysis of the power consumed as well as thermal information for the specified operating conditions.
You can toggle between two different views to identify the power consumed either by type of blocks (clock trees, logic, signals, I/Os or hard IP such as block RAMs or DSP blocks) or over the design hierarchy. Both of these views enable you to perform a detailed power analysis. They provide a very efficient method for locating the blocks or parts of the design that are the hungriest in terms of power, thereby identifying places to begin power optimization efforts.