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Design Article

# Using FPGAs to solve tough DSP design challenges

## 7/23/2012 8:37 AM EDT

EXAMPLE: A DIGITAL FIR FILTER
One of the most widely used digital signal-processing elements is the finite impulse response, or FIR, filter. Designers use filters to alter the magnitude or frequency content of a data signal, usually to isolate or accentuate a particular region of interest within the sample data spectrum. In this regard, you can think of filters as a method of preconditioning a signal. In a typical filter application, incoming data samples combine with filter coefficients through carefully synchronized mathematical operations, which are dependent on the filter type and implementation strategy, and then move on to the next processing stage. If the data source and destination are analog signals, then the samples must first pass through an A/D converter, and the results fed through a D/A converter.

The simplest form of a FIR filter is implemented through a series of delay elements, multipliers and an adder tree or chain.

Mathematically, this equation describes the single-channel FIR filter:

You can think of the terms in the equation as input samples, output samples and coefficients. If S is a continuous stream of input samples and Y is the resulting filtered stream of output samples, then n and k correspond to a particular instant in time. Thus, to compute the output sample Y(n) at time n, a group of samples at N different points in time, or s(n), s(n-1), s(n-2), … s(n-N+1), is required. The group of N input samples is multiplied by N coefficients and summed together to form the final result, Y.

Figure 2 – FIR filter of length 31

Figure 2 is a block diagram for a simple 31-tap FIR filter (length N = 31).

Various design tools are available to help select the ideal length of a filter and the coefficient values. The goal is to select the appropriate parameters to achieve the required filter performance. The most popular design tool for choosing these parameters is MATLAB. Once you have selected the filter parameters, the implementation follows the mathematical equation.

The basic steps for implementation of an FIR filter are:
1. Sample the incoming data stream.
2.  Organize the input samples in a buffer so that each captured sample may be multiplied by each filter coefficient.
3.  Multiply each data sample by each coefficient and accumulate the result.
4. Output filtered result.

A  typical C program for implementing this FIR filter on a processor using a multiply–accumulate approach is shown in the code below.

Next: Page 3

anne-francoise.pele

7/23/2012 10:30 AM EDT

Another piece, originating from the first quarter edition 2012 of the Xcell Journal, is "Embedded Vision: FPGAs’ Next Notable Technology Opportunity".

Dr DSP

7/23/2012 1:48 PM EDT

There are some very useful concepts covered here and the summary is generally spot on, however it is important to consider the DSP function in the system context.

If other functions are required in addition to the DSP it may push the solution of choice into an FPGA. For example, a low performance DSP function that is part of a sensor or motor control system need not be implemented in a stand alone DSP device. An FPGA might be the right solution in this case.

ReneCardenas

7/26/2012 11:44 AM EDT

Dr. DSP,
COuldn't the same be said in the other direction?, if there are other considerations more suitable for a DSP processor then the tilt can be as well move the other direction.
In my opinion, it has to be a case by case decision of the designer, given a set of resources and time constraints.

Just another point of view

Greg.Dee

7/26/2012 5:02 PM EDT

no offence but "For example, a low performance DSP function that is part of a sensor or motor control system need not be implemented in a stand alone DSP device. An FPGA might be the right solution in this case." doesn't make sense to me, if it's low performance you go down the performance chain, not up it. So one would consider a general micro-controller with it's obvious advantages.

glen.herrmannsfeldt

7/26/2012 3:10 AM EDT

The FIR equation is wrong.

ReneCardenas

7/26/2012 11:32 AM EDT

Glen,

It is too easy to critisize and rush to jugment in haste, when it is so easy to offer the correction of such typo that appears in many publications that are transcribed by non-technical people.
Simply stating the transgression in this case that the index coefficients are transposed for the constatnt term and the discrete variable term, would have accomplished more and been more informative to others that may not have see this simple transgression. Article as good merits otherwise, in my opinion.

nicolas.mokhoff

7/26/2012 11:51 AM EDT

ReneCardenas: your comment on striving toward positive criticism is welcome.

ReneCardenas

7/27/2012 4:29 PM EDT

Thanks Nic, that is my motto, be wise enough to know that in no way we can master the universe alone, but each of us should attempt to make the universe much friendlier place to everyone. Specially new commers to engineering.

There are lots of complexities and tough problems in the world, and nothing is gained by been destructive.

Medina

7/26/2012 11:42 AM EDT

Glen, would you care to point out the anomaly in the equation? It wasn't very evident when I looked at it.

Thanks

EricC

7/26/2012 8:52 AM EDT

Further information on how Xilinx System Generator and MathWorks HDL Coder enable Model-Based Design for targeting Xilinx FPGAs is available at http://www.mathworks.com/xilinx.

EricC

7/26/2012 8:56 AM EDT

Further information on how Xilinx System Generator and other HDL code generation tools may be used with MATLAB and Simulink -- including examples, demos, and videos -- are available from http://www.mathworks.com/fpga.

EricC

7/26/2012 10:09 AM EDT

Krutsch

7/26/2012 4:05 PM EDT

If only one would have to do FIR filters only…? Fact is the software stack is more complicated and it is really a pain to do it on an FPGA. For radar, some high end medical applications it might be a good choice.. For many , many applications it is a pain, try to get a solution certified for some automotive and avionics applications and you will see.

Alxx123

7/27/2012 12:48 AM EDT

Thats all well and good but no mention or comparison on the power used in dsp vs fpga

agk

7/29/2012 6:56 AM EDT

With FPGA's we can create massively large parallel processing so that DSP algorithms can bring useful results.

kinnar

7/29/2012 2:37 PM EDT

Actually what we are trying to implement using the FPGA is already there in DSP Processor, but what matters is the portability and the size reduction of the final product by implementing some functionality of DSP using FPGA, this way one will be able to reduce the use of DSP in many designs, but the real disadvantage of this method is it totally depends hardware dependent.