ASIC design launched for Euro space missions

PARIS – A consortium of three European companies said it will design an ASIC targeted for use in the European Space Agency's future space science and Earth observation missions.

U.K.-based SELEX Galileo and Belgium-based Caeleste and Easics said they have joined forces to develop a prototype ASIC for large format cryogenic detector arrays.


As part of the 18-month development project, Easics said it is designing the digital section using IMEC standard DARE library for radiation hardness. Easics is also in charge of the test system development. SELEX Galileo said it will provide support for cryogenic operation, test and evaluation. Then, Caeleste will be in charge of the project supervision and the design of the analog section.

Benoit Dupont, project leader at Caeleste, said infrared imaging is a key area for the company. "It is not the aim of the company to supply infrared image sensor but rather to work together with infrared image sensor suppliers to develop key circuitries to improve the overall infrared imaging chain," commented Dupont. "The development of this ASIC fits actually in that scope. Indeed, Europe has a vast offer of high-end infrared sensors both in cooled and uncooled domains. But there are very few ASICs that can handle the dataflow and supply the corresponding sequence of signals necessary to operate the sensors. This is especially true in space applications."

Dupont said consortium partners are now in the prototyping phase, which will result in a first small scale but fully functional chip by the end of the fourth quarter of 2013.

Dupont explained that the ASIC will allow cryogenic operation down to 77K but not limited to this operation. It is designed to operate as well at slightly higher temperature (120K) but also at room temperature with limited performances. This will allow system builder to tune at best their trade-off between performances and thermal budget. The aim there is to tailor the ASIC to a larger variety of devices, including CMOS and CCD image sensors with integration for instance of PGA gains in the first stage and CDS operator as well. Of course, the sequencer is programmable as well for that purpose, Dupont specified.

Asked about the ASIC availability, Dupont said it is too early to communicate on the availability of the final product but, he continued, "We could potentially provide first samples by mid or end 2015 depending on the space qualification constraints. It is designed to be industrially supplied."


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