Design Article
DO-254: Increasing verification coverage by test
Louie De Luna, Aldec, and Randall Fulton, FAA
1/9/2013 8:47 AM EST
Increasing verification coverage by test
Below is a list of recommendations that can be implemented to increase verification coverage by test. The list of recommendations proposes a methodology that can leverage the same test cases and test inputs for simulation and device testing allowing for a much stronger argument of verification fidelity and validity to the certification authority.
1. Write the requirements such that they are verifiable at the FPGA pin level. This ensures that the inputs are controllable and the outputs are observable so that each requirement can be verified by test at the pin level.
2. Create test cases based on the requirements, not based on the design. Test cases describe how to verify the requirements. Test cases define the initial setup conditions, the input conditions and the expected results for outputs and the pass/fail criteria. In addition to normal range tests, robustness tests for abnormal inputs should also be added.
3. Create the HDL testbench to implement the test cases for simulation. The inputs from the test case are applied to the HDL design and outputs are collected via waveforms. Self-checking testbenches can also be employed to automate checking for PASS/FAIL results. Ensure that any tool qualification issues are addressed and adequate logging is used for automated verification tools.
4. The testbench can be used for functional simulation and code coverage analysis. The same test vectors are used for functional simulation, functional simulation with coverage metrics, post-layout timing simulation and for device testing.
5. Use the test vectors for MIN/TYP/MAX post-layout timing simulation of the design.
6. Test the target device in isolation, at-speed, with the test vectors as test inputs. Ensure that the hardware testing setup provides 100 percent input controllability and output access points, so that the same test cases used for simulation are used for hardware test. Further efficiencies can be achieved if device testers used are able to generate results viewable in simulator waveform viewer. This way, simulation waveforms can be compared easily with device testing waveforms.
7. After testing the target device in isolation, proceed to final board testing with the flight configuration of the board to verify board level functions, components interfaces and environmental requirements.
Figure 3: Increasing verification coverage by test
Below is a list of recommendations that can be implemented to increase verification coverage by test. The list of recommendations proposes a methodology that can leverage the same test cases and test inputs for simulation and device testing allowing for a much stronger argument of verification fidelity and validity to the certification authority.
1. Write the requirements such that they are verifiable at the FPGA pin level. This ensures that the inputs are controllable and the outputs are observable so that each requirement can be verified by test at the pin level.
2. Create test cases based on the requirements, not based on the design. Test cases describe how to verify the requirements. Test cases define the initial setup conditions, the input conditions and the expected results for outputs and the pass/fail criteria. In addition to normal range tests, robustness tests for abnormal inputs should also be added.
3. Create the HDL testbench to implement the test cases for simulation. The inputs from the test case are applied to the HDL design and outputs are collected via waveforms. Self-checking testbenches can also be employed to automate checking for PASS/FAIL results. Ensure that any tool qualification issues are addressed and adequate logging is used for automated verification tools.
4. The testbench can be used for functional simulation and code coverage analysis. The same test vectors are used for functional simulation, functional simulation with coverage metrics, post-layout timing simulation and for device testing.
5. Use the test vectors for MIN/TYP/MAX post-layout timing simulation of the design.
6. Test the target device in isolation, at-speed, with the test vectors as test inputs. Ensure that the hardware testing setup provides 100 percent input controllability and output access points, so that the same test cases used for simulation are used for hardware test. Further efficiencies can be achieved if device testers used are able to generate results viewable in simulator waveform viewer. This way, simulation waveforms can be compared easily with device testing waveforms.
7. After testing the target device in isolation, proceed to final board testing with the flight configuration of the board to verify board level functions, components interfaces and environmental requirements.
Figure 3: Increasing verification coverage by test
|
|
|
|
|
Navigate to related information