Darpa to fund chip research consortium

PORTLAND, Ore. – A government-industry initiative called the Semiconductor Technology Advanced Research network will seek to maintain U.S. leadership in microelectronics.

STARnet  aims to define a successor to today's complementary metal-oxide semiconductor (CMOS) technology through a five-year, $194 million cooperative effort between academia, government and industry directed by the Semiconductor Research Corporation (SRC) with funding from the Defense Advanced Research Projects Agency (Darpa). 

Consortium members include Applied Materials, GlobalFoundries, IBM, Intel, Micron Technology, Raytheon, Texas Instruments and United Technologies.

"We are looking beyond the end of the technology roadmap for CMOS, firstly for device technologies to replace traditional CMOS, and secondly for system design methodologies that work with these new device technologies," said Gilroy Vandentop, SRC’s executive director for STARnet. Three device and three design centers were selected to push technology development.

STARnet funding totaling about $40 million annually will be divided among these six regional research centers to be located at the University of California at Berkeley and Los Angeles, University of Illinois, University of Michigan, University of Minnesota and Notre Dame. About 145 research professors and 400 graduate students are expected to work on the program. 

"Besides advances in electronics technologies, another benefit of STARnet will be education, since it will supply a steady stream of highly trained EE, computer science and physical science graduate students to the U.S. workforce," said Vandentop (below).



The Center for Spintronic Materials, Interfaces and Novel Architectures at the University of Minnesota will target new spintronic materials, devices, circuits and architectures.

The Center for Function Accelerated nanomaterial Engineering at UCLA will focus on unconventional atomic-scale materials and structures, including multifunction oxides, metals and semiconductors that can accelerate analog, logic and memory devices.

Notre Dame’s Center for Low Energy Systems Technology will concentrate on new materials and devices for ultra-low-voltage transistors while the Center for Systems on Nanoscale Information fabriCs at the University of Illinois develops nanoscale fabrics that use statistical properties of materials to provide energy efficiency beyond the capabilities of CMOS .

The Center for Future Architectures Research at the University of Michigan will focus on scalable computer architectures that leverage next-generation circuit fabrics.  Finally, the TerraSwarm Research Center at UC-Berkeley will develop  distributed sense-control-actuate technologies executed by shared, massively parallel, heterogeneous “swarm” platforms, program officials said.

Related stories:

SRC clears path to 14-nm with directed self-assembly

Research consortium claims solution for multi-core scaling