Design Article
Implementing analog functions in rugged, rad-hard FPGAs
Allan Chin and Luciano Zoso, Stellamar
2/11/2013 2:21 PM EST
Pulling analog functions onto the FPGA
Regardless of how you define “analog” and “digital,” significant differences and integration issues exist between the two. Because of these issues, it can be very advantageous to have digital designers pull analog functions onto an FPGA and test them. Herein, we will define “digital” as using standard digital library cells and passive components for a fully synthesizable and digitally testable design. Designers can create digital IP blocks of ADCs, DACs, DC/DC converter controllers and clock multipliers in RTL format and implement them in all-digital processes.
With these IP blocks, military designers can take advantage of rugged and radiation-hardened FPGAs to implement customized analog functions. Not only does this approach leverage the inherent protection properties of the FPGA, but these blocks are also a great way to utilize unused FPGA resources. Xilinx recognizes this advantage and now partners with Stellamar to provide these functions. Increasingly, aerospace companies are turning to these solutions to attack analog-integration problems.
Digital ADC core yields benefits
Figure 1 depicts an example block diagram of a Stellamar Digital ADC IP core. With the digital approach, the core requires only a few external passive components. The IP core is instantiated right inside the FPGA and is easy to implement through digital synthesis. On a Xilinx Virtex-5QV device, a scenario such as that pictured in Figure 1 utilizes less than 1 percent of FPGA resources.
Proprietary signal processing makes it possible to replicate analog sigma-delta ADC performance with all-digital library cells. Companies like SEAKR Engineering and the Finnish Meteorological Institute are using Digital ADC IP in their On Board Processor Program and Lunar Landing Missions, respectively. Some benefits are:
Regardless of how you define “analog” and “digital,” significant differences and integration issues exist between the two. Because of these issues, it can be very advantageous to have digital designers pull analog functions onto an FPGA and test them. Herein, we will define “digital” as using standard digital library cells and passive components for a fully synthesizable and digitally testable design. Designers can create digital IP blocks of ADCs, DACs, DC/DC converter controllers and clock multipliers in RTL format and implement them in all-digital processes.
With these IP blocks, military designers can take advantage of rugged and radiation-hardened FPGAs to implement customized analog functions. Not only does this approach leverage the inherent protection properties of the FPGA, but these blocks are also a great way to utilize unused FPGA resources. Xilinx recognizes this advantage and now partners with Stellamar to provide these functions. Increasingly, aerospace companies are turning to these solutions to attack analog-integration problems.
Digital ADC core yields benefits
Figure 1 depicts an example block diagram of a Stellamar Digital ADC IP core. With the digital approach, the core requires only a few external passive components. The IP core is instantiated right inside the FPGA and is easy to implement through digital synthesis. On a Xilinx Virtex-5QV device, a scenario such as that pictured in Figure 1 utilizes less than 1 percent of FPGA resources.
Figure 1: An example of a fully digital ADC IP core interface
Proprietary signal processing makes it possible to replicate analog sigma-delta ADC performance with all-digital library cells. Companies like SEAKR Engineering and the Finnish Meteorological Institute are using Digital ADC IP in their On Board Processor Program and Lunar Landing Missions, respectively. Some benefits are:
• 50 percent lower power than analog ADC parts
• 68 percent smaller area than analog ADC parts
• Process technology independence
• Reduced risk and cycle time
• Digital integration, synthesis and testing
• Easier radiation-hardened design
|
|
|
|
|
Navigate to related information