Digital clocking solutions
Phase-locked loops are some of the most widely used analog blocks for clock generation; thus, most FPGAs have incorporated PLL capability within the package. However, some FPGAs, including certain radiation-hardened FPGA families, do not include PLLs at all. Other radiation-hardened FPGAs generally do not include the PLLs in the rad-hard portion of the package.
Digital clock multiplier IP used on these FPGAs can provide the ability to generate any clock up to about 2 GHz with no lock time. Models show 50-picosecond peak and 35-ps RMS, with 5-ns to 1-ns rise/fall. As with Digital ADC IP, this solution requires very few off-the-shelf passive components.
Putting it together
Historically, FPGAs did not lend advantages to analog functions, forcing high-reliability design teams to use non-optimal external analog parts. This is no longer the case, as mil/aero engineers now have robust options for integrating analog functions into any digital fabric, including radiation-hardened FPGAs. By using digital implementations of analog functions from Stellamar, engineers can add critical functionality such as thermal monitoring, redundant power supplies and clocking functions–all without adding weight, power or size to the design. The digital synthesis and test methodology ensures the operability and greatly increases reliability.
Further, designers can easily leverage these technologies across projects and across the whole organization. With budgets being slashed and performance more important than ever, these digital IP cores give mil/aero engineering teams the flexibility and productivity they need to meet critical mission objectives.
About the authors
is CEO of Stellamar
is CTO of Stellamar
For more information about Stellamar cores, call (480) 664-9594 or go to www.stellamar.com.
This article was originally published in the first quarter issue of the Xcell Journal,
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