The most interesting innovation will be the metal contacts in the memory array. Samsung promises metal storage node and bitline contacts at 56 nm. Polysilicon plugs are now the norm for transistor and capacitor contacts in the DRAM array for every manufacturer. Transistor source/drain regions are formed by outdiffusion of dopants from the highly doped polysilicon.
Tungsten provides lower resistance, which is why it's used just about everywhere else in the industry--including the contacts to peripheral FETs in a DRAM. Samsung reports that the breakdown voltage for transistors with metal contacts is comparable with those seen with polysilicon plug contacts in a similar configuration while cutting contact resistance in half.
56-nm production will add immersion lithography to the mix of ArF and reticle enhancement techniques used today. Semiconductor Insights' latest analysis detected a 61-nm half-pitch of active area patterning proving that Samsung already employs double patterning at the OD level of their 68-nm device. There was a lot of hype about Intel using double patterning on its Penryn microprocessor, but it was already in use for this DRAM packaged five weeks before the Intel 45-nm unit.
The critical limit to shrinking a DRAM design is how leaky the access transistor is compared with how much charge the capacitor can store. Semiconductor Insights extracted a complete set of transistor performance data from the 68-nm S-RCAT. Leakage measured 2.5nA/µm at room temperature.
Samsung achieved 10.4 Mb/mm2 at 80 nm and improved that to 14.7 Mb/mm2 at 68 nm. Based on the projections and an expected cell size of 0.019µm2, we can expect to see the 56-nm generation of DRAM reach 20 Mb/mm2 squeezing 2 Gb onto a single die.
It would be unwise to doubt Samsung's ability to continue on this density path. The company aggressively scaled sense amp transistor gate lengths from 0.22µm to 0.12µm in the move from 80 nm to 68 nm. With the raised source/drain transistor at 56 nm, Samsung reported NMOS drive current of 440µA/µm. That level of performance will give designers the option of continuing to reduce area or optimize for higher performance.
When 56-nm DRAM finally hits the street, Semiconductor Insights will confirm what Samsung has claimed. Our upcoming investigation will check key details Samsung mentioned in its VLSI 2007 paper. We will test the access transistor drive current and leakage performance with nanoprobing. We will also provide 2-D carrier profiling of the S-RCAT with Scanning Capacitance Microscopy (SCM) to reveal the technology enabling Samsung's claimed drive current improvements.
Beyond 56 nm, we can look forward to a brave new world in DRAM. Samsung was the first to introduce a 3-D transistor when the 90-nm DRAM launched the RCAT structure. Samsung's peers at Hynix announced they will be going a step further with the 3-D transistor that we have heard everyone talking about for years--the FinFET. Samsung presented a FinFET for flash at the 32-nm node. Based on this, expect to see the very first FinFETs in Hynix DRAM, followed by Samsung flash chips.
Don Scansen (firstname.lastname@example.org) is semiconductor technology
analyst at Semiconductor Insights, a TechInsights company. He holds a Ph.D. from the University of Saskatchewan.