Why equalization now matters more than ever

When equalization is applied at the receiver it is possible to calculate the required filter response from the incoming data stream without the need for embedded coding or signalling protocols. This process is known as adaptation and the receiver system as an adaptive equalizer. Assuming that the adaptation algorithms are sufficiently fast, they can track time varying ISI and maintain signal quality where a fixed filter would not. When equalization is applied at the transmitter it is frequently termed pre-emphasis or de-emphasis. Although pre-emphasis cannot be adapted without a protocol to communicate the channel characteristics, it is widely used in channels where the channel response is sufficiently well known in advance. Most copper channels fall in this category and cable and backplane equalisers frequently employ pre-emphasis on their transmit stages (See Figure 2).

With advances in IC technology and design expertise ISI compensation at ultra high data rates is being achieved with electronic equalisation (called electronic dispersion compensation, or EDC) at low cost and power through optimised mixed signal equaliser architectures. The leading ICs consume little power and have very robust algorithms that make the devices easy and reliable to use, allowing them to dramatically boost performance in cost sensitive high volume applications. Adaptive equalisation now enables 10Gbps backplane links of more than 1m or copper cable links up to 30m--ideal for the majority of data-centre applications. This technology also extends old FDDI grade optical fibre reach to 220m at 10Gbit/s through the 10GBASE-LRM standard, allowing existing infrastructure to be upgraded to higher data-rates without installing new optical cabling.

Different approaches
There are several different techniques available for equalisation, all with different engineering trade-offs in power consumption, performance and cost.

The simplest approach is Feed Forward Equalization (FFE). This employs a finite impulse response filter (FIR) with a series of tap weights programmed to adjust the impulse and, by duality, frequency response (See Figure 3). This is the simplest implementation and can be designed entirely in the analogue domain. Such an approach lends itself to very high speed and usually offers relatively low power. However, FFE also offers limited performance, insufficient for the majority of 10Gbps systems.

Perhaps the most complex approach is Maximum Likelihood Sequence Estimation (MLSE). This technique immediately converts the signal from analogue to digital and processes the signal digitally using a Viterbi decoder in combination with channel estimation to recover the most probable transmitted symbols. This approach offers very good performance, but at 10Gbps requires more cost and power than is economic for broad deployment.

The middle ground is occupied by Decision Feedback Equalization (DFE) (See Figure 4). This architecture lends itself well to mixed signal designs that can approach the performance of MLSE equalization while only requiring a little more power and cost than FFE approaches. Implementations in CMOS lend themselves well to technology scaling and integration into ASIC I/O structures, making this a popular architecture. However, extracting good performance from DFE architectures depends on a high quality implementation. Key parameters include; a highly linear signal path, a broad and flat frequency response and low equivalent input noise. In addition to these performance parameters are a number architectural features that influence the capability and ease of use. These include synchronous versus asynchronous delay elements, number of feed forward and feedback taps and the stability and accuracy of the adaptation algorithms.