When equalization is applied at the receiver it is possible to calculate the required filter response from the incoming data stream without the need for embedded coding or signalling protocols. This process is known as adaptation and the receiver system as an adaptive equalizer. Assuming that the adaptation algorithms are sufficiently fast, they can track time varying ISI and maintain signal quality where a fixed filter would not. When equalization is applied at the transmitter it is frequently termed pre-emphasis or de-emphasis. Although pre-emphasis cannot be adapted without a protocol to communicate the channel characteristics, it is widely used in channels where the channel response is sufficiently well known in advance. Most copper channels fall in this category and cable and backplane equalisers frequently employ pre-emphasis on their transmit stages (See Figure 2).

With advances in IC technology and design expertise ISI compensation at ultra high data rates is being achieved with electronic equalisation (called electronic dispersion compensation, or EDC) at low cost and power through optimised mixed signal equaliser architectures. The leading ICs consume little power and have very robust algorithms that make the devices easy and reliable to use, allowing them to dramatically boost performance in cost sensitive high volume applications. Adaptive equalisation now enables 10Gbps backplane links of more than 1m or copper cable links up to 30m--ideal for the majority of data-centre applications. This technology also extends old FDDI grade optical fibre reach to 220m at 10Gbit/s through the 10GBASE-LRM standard, allowing existing infrastructure to be upgraded to higher data-rates without installing new optical cabling.

Different approaches
There are several different techniques available for equalisation, all with different engineering trade-offs in power consumption, performance and cost.

The simplest approach is Feed Forward Equalization (FFE). This employs a finite impulse response filter (FIR) with a series of tap weights programmed to adjust the impulse and, by duality, frequency response (See Figure 3). This is the simplest implementation and can be designed entirely in the analogue domain. Such an approach lends itself to very high speed and usually offers relatively low power. However, FFE also offers limited performance, insufficient for the majority of 10Gbps systems.

Perhaps the most complex approach is Maximum Likelihood Sequence Estimation (MLSE). This technique immediately converts the signal from analogue to digital and processes the signal digitally using a Viterbi decoder in combination with channel estimation to recover the most probable transmitted symbols. This approach offers very good performance, but at 10Gbps requires more cost and power than is economic for broad deployment.

The middle ground is occupied by Decision Feedback Equalization (DFE) (See Figure 4). This architecture lends itself well to mixed signal designs that can approach the performance of MLSE equalization while only requiring a little more power and cost than FFE approaches. Implementations in CMOS lend themselves well to technology scaling and integration into ASIC I/O structures, making this a popular architecture. However, extracting good performance from DFE architectures depends on a high quality implementation. Key parameters include; a highly linear signal path, a broad and flat frequency response and low equivalent input noise. In addition to these performance parameters are a number architectural features that influence the capability and ease of use. These include synchronous versus asynchronous delay elements, number of feed forward and feedback taps and the stability and accuracy of the adaptation algorithms.

Synchronous versus asynchronous delays
The delay elements in the equalizer can be implemented with simple analog time delay elements implemented using passive components such as inductors and capacitors. The time delay here depends on component values which vary with process and temperature that are unrelated to the incoming data rate. As a consequence, it is not possible to time align all filter taps optimally. In the worst case, a tap may be sampling the signal during a transition, in which case the tap merely adds noise to the output signal. To overcome this problem, asynchronous equalizers often include two or more taps per bit period. This ensures sufficient samples that include near maximum signal energy. Synchronous equalizers, by contrast, recover a clock and use this to shift the data through clocked delay stages. This approach can guarantee optimum sampling for every tap, minimising the number of tap stages required. While synchronous architectures offer excellent performance, they require clock recovery directly from highly dispersed data, which mandates a very high performance clock recovery unit, often incorporating sophisticated phase detector architectures.

Adaptation algorithms
Adaptive equalizers need to calculate an accurate estimate of the channel transfer characteristic in order calculate the compensating tap weights. The algorithms that perform these calculations depend on the metrics used to measure the incoming data. These have a dramatic impact on the ease of use and performance of the equalizer circuit. A high performance signal path is of little use if the controlling algorithms diverge or get stuck in a local minimum that fails to properly correct the signal. Algorithms running on external microprocessors will be much slower than integrated hardware algorithms and can dramatically increase the cost, power and complexity of an equalizer solution. Most modern adaptive equalisers should have built in algorithms that are stable and easy to use.

Pre-emphasis
As mentioned earlier, for copper channels, including cables and backplanes, pre-emphasis at the transmitter can pre-distort the signal in order to counter the high frequency loss of the channel. Alternatively, a communication protocol can be established between the receiver and transmitter. In this way, the receiver can "instruct" the transmitter to adjust its pre-emphasis to optimise the signal at the receive location. Such an approach has been adopted in the IEEE 10GBASE-KR standard for backplanes.

Conclusion
Equalization is a well-established technique for coping with ISI at lower data rates, but is now bringing the advantages of longer reach and lower power to a wide range of serial communication applications that enable the 10Gbps speeds modern systems increasingly demand. Equalization is enabling everything from high speed memory buses and blade server backplanes through to copper and fibre optic data centre interconnects. This trend is being encouraged by shrinking CMOS geometries and standardization of interfaces allowing interoperability between vendors. As the insatiable demand for bandwidth continues apace, the high-speed equalization technologies being pioneered today will move further into the mainstream of the communications systems of tomorrow.

About the Author
Paul Denny is a founder member of Phyworks with in-depth experience of high frequency IC design and product management. Before joining Phyworks he was Director of Engineering at Microcosm Communications, where he was responsible for the development of optical transceivers and PMD devices. His previous experience includes eight years spent in the San Francisco Bay area developing CMOS frequency synthesizers for wireless communications. He has previously worked at National Semiconductor, Nortel Networks and Zarlink. Paul has been awarded a significant number of patents during his career.