Protecting the HDMI interface

"Ease of use" for such a complex interface implies a certain durability and ruggedness in the consumer electronics environment. Delicate signaling and precise protocols must endure serious misuse without complaint. For example, the "same connector on each end" implementation mimics the simplicity of RCA phono jacks, which can be plugged into illegal configurations via "adapter" cables, or can be used to connect two outputs together erroneously. Additionally, for any I/O signal exposed to the outside world, ESD strikes are a constant danger during interconnection. A single spark can render an entire entertainment system useless.

The high-performance digital imaging silicon ASICs required for these applications usually include some protection sufficient for a controlled manufacturing environment. But the physics of their deep sub-micron fabrication geometry must be optimized for performance, not ruggedness, and is no match for the uncontrolled ESD environment of the end-user. Therefore, even the most basic HDMI port implementation for these applications necessarily entails multiple external interface and protection circuits. The diagram below shows a discrete implementation of all the necessary and desirable interface protection and isolation functions.

Here, each TMDS line is protected from ESD with a low-capacitance Dual Rail Clamp diode pair that routes negative ESD pulses directly into ground, and positive pulses back to ground through a zener diode. Each of the signal lines exposed to the HDMI connector are protected in this manner. All of these clamps are further prevented from providing a DC backdrive path through a blocking circuit from the biasing supply.

In the discrete schematic above, there are hidden implementation pitfalls that may not be initially obvious. These potential hazards include impedance and layout tuning for TMDS lines, appropriate threshold voltages and RDS(on) characteristics of level shifting N-FETs, ESD clamp levels, response times and matched parasitic inductance, overcurrent protection for outputs, and backdrive protection for all signals.

Successful high speed TMDS differential signal routing is a complex system design challenge in itself. Adding even the most minute parasitic loading for ESD protection to these finely tuned transmission lines can often be the difference between pass or fail. The resulting transmission line characteristics and impedance matching cannot be easily predicted from mere component level specifications, and indeed, some counter-intuitive results may be observed. For example, adding trace inductance or stubs can, in certain cases, actually improve the characteristic impedance of the line while retaining optimal ESD clamping.

ESD protection and backdrive protection are important on each and every external signal line, especially with multiple power domain entertainment systems (DVD, HDTV, Satellite Receiver, Audio Decoders, etc.). While the need for ESD clamps on exposed signal lines is obvious, the potential for backdrive and its ill effects is not always apparent, even with rigorous system testing. Early PCs with CMOS parallel ports experienced this problem with certain printers upon the advent of soft power management. Upon entering power-saving states, the PC would shut down its internal power planes -while external peripherals- such as printers, were still powered from their own sources. In some cases, often via output ESD clamps, a forward biased path was energized that could "charge" the bulk capacitance of the internal power planes with mere milliamps. This unexpected voltage level could cause problems with Power-On-Reset circuits causing the system to hang on recovery from standby states. Obviously, in the modular digital entertainment systems enabled by HDMI, this potential complication with independent power management also exists.

TMDS PROTECTION

A dual-rail clamp ESD protector's primary function is to shunt high-voltage ESD current pulses off of the TMDS node by presenting a very low impedance dynamic path to ground, minimizing the I_RESIDUAL current that delicate HDMI or DVI PHY logic must dissipate.

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During normal operation, though, it is imperative that the impact of the parasitic inductance and capacitance of the ESD device be minimized.

The channel capacitance of the reverse biased ESD clamp diodes and the parasitic series inductance of the package leads and bond wires (shown below) create a lumped resonant LC tank circuit that creates a low impedance shunt at the natural self-resonance frequency of the device.

The impedance at this resonant frequency and the quality factor (Q) of the insertion loss notch determine how much this resonance point will distort the signal. The following plot shows the range of possible resonant frequencies for a SOT23-6 package with 1.0 to 1.5pF of channel capacitance (approx 3.1GHz with 1.5pF to 4.2GHz with 1.0pF).



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The maximum transition rate of the data on a TMDS pair at 165MHz is 1.65GHz (with a square wave having odd harmonics at 4.95GHz, 8.25GHz, and so on.)

The extent to which the parasitic self-resonance notch attenuates the spectral components of the signal non-linearly determines the amount and shape of the deformation of the resultant waveform. (Increasing {GRN/BLU/AQUA} effect of parasitic capacitance shown below on a 1.65GHz square wave.)





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The actual parasitic model of a protection component has multiple elements, in addition to the complex and difficult to control PCB elements. The "GROUND" of the protection device is isolated from the "GROUND" on the PCB and is yet again isolated somewhat from the Return "GROUND" at the HDMI connector. The self-resonance frequency and thus the parasitic insertion loss notch can be moved higher by minimizing the inductance in this return path via optimization of the ground paths in the protection IC(s). Increasing the number of paralleled ground pins on a given package, for example, can help in this manner.



The complexity of these factors, hidden by the simplicity of a schematic diagram, are obviated in the following 3D depiction of a protection integrated circuit. The elevated lead frame shape, the permeability of the plastic molding, the height of the silicon die and of course wire bond diameter and length are all contributing factors to the resulting parasitic impedance and RF frequency response of the high-speed traces.



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