Tip of the Week: How to solve for LDO regulator-enabled glitch

Enable Glitch Issue
The operation of a LDO regulator is controlled through an enable pin. The voltage domain (1.0V as an example) of an external control circuit may be lower than that (minimum 2V as an example) of the regulator. Thus an enable circuit is an essential part of a regulator. As shown in Fig.1 (a), a larger resistor R1 is normally connected between V_dd and the source of PMOS transistor in the input inverter of the enable circuit. Under stable condition of V_DD, if the regulator needs to be enabled, V_{enable_in}=1V (higher than the threshold voltage of the NMOS transistor) and both N1 and P1 turn on. But R1 acts as a current limit resistor, the output of this stage is still nearly at 0V. Therefore V_{enable_out}=V_DD, and the regulator is enabled.

However, as power supply V_dd(t) is ramped up from 0V with a disabled signal at the input of the enable circuit (V_{enable_in}=0V), the transient source voltage V_s1(t) of P1 is less than V_dd(t) for a period of time due to the existence of R1, and both N1 and P1 turn off before the gate-source voltage V_gs1 of P1 reaches Vtp (the threshold voltage of PMOS transistor). During this period of time, the output of this stage is still at 0V rather than at V_dd(t). Thus V_{enable_out}=V_dd(t) and the regulator is enabled, resulting in an unwanted turn on of the regulator as V_dd(t) ramps up. A larger resistor R1 makes this situation even worse.

Solution
A solution to this problem can be seen in Fig.1 (b). P5 is connected between V_dd and a control point Vc. Small capacitor C1 (5pF as an example) is connected between Vc and ground. As V_dd(t) rises initially from 0V (V_{enable_in} is kept at ("0"), Vc is 0 and does not increase until V_dd(t) increases to over the threshold voltage |Vtp| of P5. Then Vc rises gradually due to C1. During this period, the pull-up transistors P2 and P3 controlled by Vc turn on and conduct a transient current. This transient current ensures a "low"(disabled) output at V_{enable_out}. The width of P2 and P3 is designed to be smaller than that of P5 to guarantee no glitch when there is a line transient during normal operation. Another small capacitor C2 (5pF as an example), connected between V_dd and Vc via P4, is also for this purpose. P4 is controlled by the inversion state of V_{enable_out}, so that C2 is only in use during normal operation (enabled) of the regulator. If V_dd increases sharply, such as a line transient, in normal operation, C2 will force Vc to follow V_dd quickly and there will be no transient current following through P2 and P3 in this case. Without C2, a disabled signal (glitch) will be generated at V_{enable_out} when V_dd increases transiently and significantly during normal operation. P6 is used to discharge Vc after V_dd drops to 0V (turned-off). Vc can also be charged via the drain-body diode of P5 when _dd=0V.

Figure 1. Previous enable circuit (a) and improved LP3991 enable circuit (b)

Three Test Results
Based on National's LP3991, 3.3V LDO regulator samples with the old and new enable circuit employed are tested under the condition of the enable pin connected to ground (disabled, there should not be output voltage for the regulators) during V__in (V) ramped up. The outputs of the LDO samples with both old and new enable circuits are labelled as V_{_out(old)} and V_{_out(new)} respectively.

Without load, test results are show in Fig.2. Fig.3 shows the test results for both samples with 1K-ohm resistor connected at outputs (3.3mA load current). It is clearly seen 1.4V output appears at the output of the old sample and lasts for a long time when no load applied and lasts for about 2ms when a 1k-resistor load applied. The improved circuit does not show the glitch problem.

About the Author
Shengming Huang is a lead designer for power management product development in National Semiconductor's Design Center in the UK. He has more than 10 years of experience in power electronics and analog design. He holds eight voltage regulator related U.S. patents and has published more than 30 papers mostly in the area of high power electronics. He develops high performance capacitor-free LDO regulators. He received his B.Sic degree from Hefei University of Technology, M.Eng degree from Xian Microelectronics Institute, and PhD degree from Cambridge University.. Shengming can be reached at: shengming.huang@nsc.com.