FLEX Protocol Delivers De Facto Messaging Standard for Handhelds

Pagers and embedded messaging have become mainstream portable applications. They send digital messages to central base stations that dispatch the information to other locations. New, de facto messaging standards have emerged to provide the underlying messaging mechanisms to drive these applications that range automatic utility meter readers and smart vending machines to automobile security systems. One key de facto standard is Motorola's FLEX protocol, a one-way paging protocol.

The FLEX protocol can be implemented in a hardware core integrated with low-power RISCs. Motorola engineers have implemented a FLEX decoder core and integrated it with the M•CORE, mini-RISC architecture. This implementation can be deployed as the core processor for low-power, handheld applications. The SoC incorporates the FLEX protocol and its software stack.

Currently, 229 operators in 48 countries, representing over 92% of the world's paging subscriber base, are in commercial operation with the FLEX protocol or in the process of bringing it online. And Japan, Korea, India, China, and Russia have also adopted the FLEX protocol as their national standard for high-speed paging.

The entire paging process is based on the production of some form of selective signaling (coding) format that will initiate an alert in one specific receiving device (or possibly a group of these devices). It also provides a format in which to deliver some form of message to that device, the pager. The key element in this process is a format that performs the transfer of information in an efficient and effective manner.

Historically, several formats have evolved to provide this service such as an early analog two-tone and 5/6 tone sequential formats. While effective, these formats were limited in system capacity, throughput, and functionality. To satisfy the increasing demands for paging services, the industry turned to true digital formats. Several formats evolved from this need, such as the Golay Sequential Code (GSC) and the Post Office Code Standardization Advisory Group (POCSAG) protocols.

This evolution in signaling formats once again has been driven by the increasing popularity of paging as a personal communications tool. The FLEX protocol for high-speed paging supports increased transmission speed and capacity. Service providers have adopted the protocol because it quadruples the capacity of other paging protocols and significantly improves messaging reliability.

Thus, the FLEX family of wireless transport protocols greatly enhances the channel efficiency and the cost of traditional paging systems while enabling new value-added wireless services. There are two Messaging Systems currently defined, the FLEX (one-way data messaging) protocol and the ReFLEX (two-way data messaging) protocol.

FLEX-based protocols provide higher transmission speeds than the older protocols. The FLEX protocol builds upon existing systems using POCSAG 1200 and runs side by side with POCSAG on one RF channel. Current 1200-bps POCSAG systems have a channel capacity of approximately 120,000 numeric pagers per channel. The FLEX protocol provides paging speeds up to 6400-bps to allow more than 600,000 numeric pagers per channel.

The FLEX protocol maintains data integrity by providing error protection against multi-path fading errors (caused by multi-casting), and by keeping the data-reception electronics continuously in synchronization with the transmission. It also provides roaming capabilities and significantly improves product battery life.

The FLEX paging protocol is a synchronous time-slot protocol that is referenced to an accurate real-time base, the Global Positioning System (GPS). Each pager implementing the protocol is assigned to a base frame in a set of 128 frames (0-127) transmitted during a 4-minute time interval called a cycle (32 frames-per-minute, 1.875 seconds-per-frame).

Fifteen FLEX cycles (numbered 0-14, cycle 0/frame 0) occur each hour and they are synchronized to the start of the GPS hour. The FLEX pager's capcode defines its base frame assignment. How often the pager awakes to receive frame information is determined by the collapse value assigned to it, which affects battery life.

Figure 1: Each FLEX frame consists of a synchronization and data portion.

The synchronization portion of the FLEX frame consists of a synchronization signal and an 11-bit frame information word that allows the pager to identify the frame and cycle in which it resides uniquely. A second synchronization signal indicates the rate at which the data portion is transmitted (i.e., 1600-, 3200-, or 6400-bps). Data is transmitted using either two- or four-level frequency shift keyed (FSK) modulation. The 6400-bps rate is transmitted as four concurrent phases of information using four-level FSK modulation.

The FLEX encoding and decoding rules specify the minimum requirements that must be met by the paging device, paging terminal, or other encoding equipment to properly format a FLEX data stream for RF transmission and to successfully decode it.

The FLEX Stack One-Way (FS) simplifies the task of incorporating a FLEX protocol into a wide variety of devices and appliances to process information received and demodulated from a FLEX decoder. FS is an Application Programming Interface (API) that runs on a host processor to manage communication with the FLEX decoder. FS handles the initialization, buffering of received code words, and decoding of separate address, vector, and data packets. It also performs phase de-multiplexing, roaming, security, and event notification (out of range, low battery, time of day, and error conditions).

Figure 2: The FLEX Stack One-Way Version 4.1 consists of three modules and public and intermodule application program interfaces that control the FLEX decoder and manage the raw FLEX data.

The Driver module manages the flow of data from the FLEX decoder and builds raw message data from received data streams. The Message manager module stores and manages message data and routes calls to the appropriate API. The Message filter module formats raw message data according to the required format. This format could be ASCI characters, binary data, ideographic character symbols, or any other supported form.

A Public Application Programming Interface (PAPI) complements the three fundamental FS modules. The PAPI provides a high-level interface that is used by the host software to manage message data, message notification, and the FLEX decoder using eleven function calls.

Engineers don't have to design their FLEX-based systems from scratch. Motorola engineers have developed a reference design, a FLEX application to showcase details of the FLEX protocol, hardware and software interface. This design, the MMC2080 chip, integrates several field-proven technologies, providing a versatile Roaming FLEX solution. This device combines the control and I/O capability of an M•CORE RISC processor with the processing power of the Roaming FLEX Alphanumeric Decoder core.

The design features an integrated FLEX protocol decoder, digital demodulator, alert generator, and time-of-day timer. These features make this device ideal for mid-tier pagers and advanced messaging solutions.

The FLEX decoder in the MMC2080 is the G1.9 compliant version for roaming, allowing paging carriers to network many paging systems across a broad geographic region and provide complete service to the customers who want nationwide service, all without disrupting service to existing local customers. This feature is important in countries like China and Korea that operate on different frequencies from region to region.

In addition to the roaming capability, the FLEX G1.9-compliant decoder features partial addressing that increases battery life up to 25% and an internal demodulator that eliminates the need for a discrete analog-to-digital converter.

Figure 3: The MMC2080 SoC implements a low power M•CORE RISC processor with 24K x 32 bits of ROM (96K bytes) and 1.5K x 32 bits of RAM (6K bytes).

The M•CORE processor is a streamlined execution engine that provides many of the same performance enhancements as mainstream RISC architectures. It is implemented with a fixed 16-bit instruction length and 32-bit internal data path. Its 16-bit instruction/32-bit data word provides a high degree of code density, minimizing both the need for memory and the overhead of memory system energy consumption.

To provide optimal static power management for the overall system, the M•CORE processor provides three instructions (stop, wait, and doze) that enable external logic to disable power to parts of the system. These instructions provide power management to internal peripherals as well by shutting down unused circuits that are not needed while waiting for the pager's particular frame.

The M•CORE processor communicates through the APB Peripheral Bridge, which is the interface between the system bus and the peripheral bus. Operation of the APB is completely automatic and does not require any programming. The M•CORE processor and its associated peripherals have both doze and stop low-power standby modes. Through the System Integration Module it is possible to place many of the individual modules on the MMC2080 into one of the low power modes independent of one another, thus providing the greatest possible flexibility in power saving.

The FLEX decoder simplifies implementation of a FLEX paging device by interfacing with most industry-standard paging receivers. Its primary function is to process information received from a FLEX radio paging channel, select messages addressed to the paging device, and to communicate the message information to the resident M•CORE processor as illustrated in Figure 4. It front-ends the M•CORE processor, off-loading the CPU from the FLEX decoding.

The FLEX decoder supports 1600-, 3200-, and 6400-bps decoding. Intermediate frequency signals are demodulated, synchronized, de-interleaved, and error corrected prior to entry into a holding buffer. The holding buffer is then fed into a synchronous serial peripheral interface (SPI) which then converts the data into a parallel format. All communication with the M•CORE processor is through the SPI control/status and data registers. The SPI is interrupt driven to reduce processor overhead and save power.

A resident real-time clock operates off a 76.8-kHz or 160-kHz crystal and is used to wake up the M•CORE processor at one-minute intervals. This permits the M•CORE processor to operate in a low power mode when monitoring a single channel for message information. A low battery detect input is also available and generates interrupts to the M•CORE processor for display of a low battery symbol on a user interface and graceful shutdown.

Figure 4: MMC2080 FLEX Decoder Block Diagram

With the MMC2080 base, developing products with messaging capabilities is now easier for the hardware and software designer. In addition, development tools are available that facilitate rapid evaluation of the FLEX protocol. The FLEX Stack Roaming protocol software has recently been ported to the M•CORE processor and is available for licensing.

The MMCCMB2080 Computer Memory Board provides an easy interface to a RF receiver and a host computer for system level prototyping. The board provides a Motorola development tools interconnect standard known as Modular All Purpose Interface (MAPI). This interface permits connecting FPGA development boards for custom circuit development.

Figure 5: An illustration of a FLEX Development Kit that is being made available.

The FLEX protocol doesn't necessarily restrict designers to one-way communication. The underlying technology of the FLEX protocol allowed for the development of the ReFLEX protocol.

The ReFLEX protocol provides an asymmetrical high capacity two-way data message delivery system for paging applications. It has a synchronous frame structure similar to and compatible with the FLEX protocol on a frame basis.

The ReFLEX protocol delivers control and data messages to subscriber units on a forward channel (outbound from the base transmitter) and receives independent acknowledgements and, from subscriber units equipped with keyboards, messages on a reverse channel (inbound from the subscriber unit to the base receiver). The ReFLEX protocol system also permits the service provider to monitor the paging devices' location within a local geographic area using subscriber unit registration.

ReFLEX systems are designed to operate on a frequency spectrum with a width that is a multiple of 25-kHz. A 25-kHz band supports a single digital FM control and data message channel, centered on the band. Digital FM channels must remain at a distance of 12.5-kHz from the edges of the available spectrum. A 50-kHz forward channel can support up to three digital FM control and data message channels separated by 12.5-kHz and operated in time lock. Outbound channels operate at the 930/931- and 940/941-mHz range and inbound channels operate at 901/902-mHz. The Motorola Page Writer 2000 two-way pager is an example of an implementation of the ReFLEX protocol.

Figure 6: The protocol supports systems consisting of up to eight forward control channels. This opens an immense number of opportunities for low cost messaging applications.

New products are easier to implement when there is a complete solution to carry you from the conceptual stage to the delivery of production units. The integration of a FLEX decoder onto a low power M•CORE micro-RISC processor, the availability of the FLEX Stack software and a suite of development tools to accelerate product development makes the MMC2080 an attractive system solution for applications that require messaging capability. Device drivers are also available for each peripheral on the MMC2080 and will be offered in a software library.