PRODUCT HOW-TO: The ARM Cortex-M3 and the convergence of the MCU market

ARM has been in the news a lot recently as they position themselves for the impending battle against Intel in the burgeoning high-end embedded processor market. Much to the delight of the trade press, Intel have turned their enormous marketing budget to focus on the embedded marketplace and it is hard to find an embedded related website that is not presently displaying Intel advertising.

At the recent Embedded Systems Conference in Farnborough, UK, the Intel versus ARM drama stole the show at the State of Microelectronics keynote.

While this is potentially an interesting story, is the real story not what is happening right now in the embedded microcontroller market? In 2007, the embedded microcontroller market was worth $26billion, shared amongst over 40 vendors of over 50 different architectures. No single vendor had more than 5 percent market share¹.

ARM launched the Cortex-M3 processor in October 2004. In March 2006, Luminary Micro (now a division of Texas Instruments) launched the first Cortex-M3 based microcontroller. STMicroelecronics followed suit in June 2007 with the extensive STM32 range. Since then, NXP, Atmel, Zilog and many others have licensed the processor.

As of March 2009, there were 28 licensees including 6 of the top 10 worldwide semiconductor companies². While a very different market, if ARM's achievements in smart phones (>80 percent market share¹ ) are anything to go by, the Cortex-M3 may spark a rapid consolidation of the microcontroller market, dramatically reducing the number of competing architectures on offer.

Why is this happening? Microcontroller vendors have traditionally competed against each other by offering a combination of features that were in some way superior to the competition in a particular niche market. A notional microcontroller feature set can be described in term of cost, power consumption, execution speed and peripheral set.

Historically it has been difficult to produce a single range of devices that can boast good performance in all of these areas as improving one tends to worsen another. In high volume designs, cost is largely dictated by gate count.

Gate count increases cost because more gates require a larger die area and package while smaller gate counts can be implemented using older, less expensive process technologies in the same package size. Power consumption is a complex area, but typically vendors have reduced gate count and clock speed amongst many other techniques in order to reduce it.

In digital electronics, most power is dissipated during the clock transitions so increasing clock speed increases power consumption. Execution speed is a derivative of clock speed, accumulator width, instruction set and numerous other factors. Increasing accumulator width and complex instruction sets add gates to a processor, thereby increasing both cost and power consumption. Similarly, feature rich peripherals and their associated SRAM buffers add gates to the design.

The original Cortex-M3 processor core has only 33,000 gates, potentially offering a very compact silicon die footprint. This fact combined with advanced low-power modes can dramatically reduce power consumption. The core can operate from 0 to 100MHz in implementations currently available. Direct memory access (DMA) enables device vendors to provide a large number of peripherals while eliminating the requirement for large SRAM buffers in each peripheral with a direct cost benefit.

The processor instruction set is known as Thumb2. In the past, ARM processors could execute 32 bit ARM instructions or 16 bit Thumb instructions. The ARM instructions were more feature rich and hence enabled faster code execution but required more storage space. The Thumb2 instruction set is a combination of 16 and 32 bit instructions designed to give an optimum balance between execution speed and code size. With processor cores getting ever smaller, flash and SRAM requirements are increasingly dictating the final device cost.

The Thumb2 instruction set is a key characteristic of the Cortex-M3 as it facilitates 32 bit execution speed with a flash requirement comparable to 16 bit designs. Some may question the description of the Cortex-M3 as a low-power processor. The term low-power, as with many things is a relative term. For the performance available, the Cortex-M3 is undoubtedly low-power when compared with many competing architectures. A feature reduced variant of the M3, the Cortex-M0 is also available with a gate count of 12,000 and a processor core that consumes as little as 85 microwatts/MHz³.