Intermediate-bus architecture solves power-conversion challenges

Voice and data communication service providers use port density and cost per port as key criteria in evaluating carrier-class communications network infrastructure equipment offerings. Equipment manufacturers respond by trying to design and deliver increasingly small, dense and low-cost systems in order to establish and maintain a competitive edge.

Increases in port density and equipment functionality introduce significant changes in the management of power and heat-dissipation strategies for the entire product design. Compounding the already challenging technical issues associated with highly dense integration, these critical power-management problems spread out beyond the envelope of historical design approaches and can be solved only with new power-management architectures that incorporate smaller and more efficient power-management devices.

Working in direct contrast to the growing need for physically smaller power supplies, three issues are conspiring to materially drive up the size of board-mounted power modules. For next-generation communications platform designs, these are:

• Current consumption: Faster and higher-performance digital computing is nearly synonymous with increased current consumption. Individual embedded processors fabricated on smaller semiconductor geometries only exacerbate the power consumption problem due to increased leakage-current effects.
• Rising functionality: Increasing functionality in the equipment, such as the ability to process video or multimedia content, is driving increased digital integration or, in some cases, actual increases in the number of digital chips required. Both are driving the need for a larger number of simultaneous discrete voltages and, hence, a larger number of power converters per system.
• Exploding variety: Proliferation of a wider variety of application-specific integrated circuits (ASICs), gate arrays and embedded processors on a wide variety of fabrication technologies has created an equally diverse set of supply voltage requirements. Heterogeneous system designs that integrate many of these devices together inherently require different voltages throughout the system and thus more power converters.

Spec tightening
In addition to the system design issues and performance requirements described above, there are some very specific technical hurdles that also must be overcome. As semiconductor process geometries continue to shrink, their required input voltages continue to get lower and lower. In addition, the regulation tolerances of those input voltages tend to get tighter and tighter on a percentage-point basis, meaning that the total absolute variance in voltage is being reduced dramatically.

With a 5-V rail, typically a tolerance of 5 percent, or 250 mV, is acceptable. But contemporary microprocessors use voltage supplies down in the 1.2-V range, with variance tolerances on the order of 2 percent, or 24 mV.

Some ASICs even have requirements on the order of 1 V and 0.5 percent, or 5 mV. These tighter specs make it difficult for a power supply to successfully and accurately regulate a local and a remote load while meeting these tolerances, since the drop across the supply trace to the remote load could easily exceed the 5-mV requirement of an ASIC design.

Cutting it down
Two approaches are available to reduce the real-estate requirements of the power-management section. The first is increased silicon-level integration of various individual power supply components. The second is increased dc/dc converter switching frequencies.

Integration has obvious benefits in reducing power supply real-estate requirements. Increases in power supply switching frequencies, however, enable new, previously unreachable levels of integration. The resulting levels of supply efficiency and the use of fewer and smaller passive components in the output filter result in significant space savings.

Another factor driving voltage accuracy is the step size of the dc/dc voltage conversion. Typically, the 48-V bus is stepped down to a 12-V intermediate bus, and all of the remaining voltages are derived from that 12-V supply.

A good rule of thumb, however, is that designers should not exceed a 10:1 ratio in stepping down dc voltages. With the 12-V rail, that rule of thumb suggests that a voltage on the order of 1.2 V should be the lowest voltage that is achievable in a robust design, primarily due to the switching-frequency duty cycle. This condition is further restricted when transient performance is a critical factor of the design. Depending on the transient-performance requirements, this ratio could be as low as 6:1 or 7:1.

With a 300-kHz pulse-width modulation (PWM) dc/dc converter, dropping from 12 V to 1 V requires a duty cycle of 8.33 percent and a pulse width of approximately 278 nanoseconds (duty cycle = Vout/Vin). If the switching frequency is increased to 1 MHz, in order to achieve the integration benefits described above, the pulse-width contraction results in an approximate 83-ns pulse width, while a 5-MHz PWM has a pulse width of less than 17 ns.

Commercially available power MOSFETs have turn-on times on the order of 150 to 200 ns and obviously cannot support the scenario above. Radio frequency (RF) MOSFETs can switch at these speeds, but are not practical for power supply applications.

Switching tactics
Clearly, as the supply voltage requirements continue progressively lower, system designers must develop a new architecture to meet the power-management design goals for carrier-class communications infrastructure equipment.

The answer is a distributed point-of-load (POL) intermediate-bus architecture based on a 5-V rail that uses smaller power devices spread around the board. This will supply local loads such as individual ASICs, gate arrays, logic or processors, and enable the use of higher switching frequencies.

The 5-V intermediate bus is recommended instead of a 7 V, 8 V or other voltage between 5 and 12 V, since it can meet the 10:1 requirement from 48 V and down to the sub-1-V range. The use of a 5-V rail also minimizes system cost, as it will reduce the number of converters required in the system by one (for example, 8-V intermediate bus to 5-V load).

To help minimize system cost, the 12-V supply should be maintained but used primarily for fans, disk drives and any other existing requirement in the system, as well as any required board voltages between 5 and 12 V. For board-mounted components, the 5-V intermediate bus should be adopted and used for supplying the remaining voltage requirements. While very application dependent, this new architecture combined with new technology now available could bring the system designer an equivalent board-mounted power system in as little as one-third the area currently required.

With a POL architecture, supply voltages are created locally — right next to the load. Therefore, the very tight voltage tolerances required for these advanced digital chips can be met very precisely. This architecture significantly helps with designing a reliable carrier-class system that has these tight tolerances by giving the designer fewer variables to consider for that specific power supply (such as overload, temperature and, especially, lifetime aging effects).

The evolution to POL is analogous to the move from shared mainframe computers to desktop computing resources; as soon as cost, performance and integration allowed it, individual computers networked together made sense. The same is true for power conversion — with the available technology, each major device in a system gets a "personal" POL supply, networked together through an intermediate-bus architecture.

Combining all the benefits of the 5-V intermediate bus with a distributed POL architecture and using advanced-technology power supply components with higher integration and higher switching speeds can shrink board size, allow more functionality to be placed on a board, simplify board layout and routing, and reduce cooling requirements. All of this leads to the capability of achieving the ultimate goal of increasing port density and functionality for voice and data communications infrastructure equipment applications.

Ashraf Lotfi (lotfi@enpirion.com) is the chief technology officer at Enpirion Inc. (Bloomsbury, N.J.).

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