Using statistical activity for power estimation

Power, among other things, is a function of operating voltage, switching capacitance, and switching activity (dynamic power = ½CV2f). Standards for capturing operating voltage and switching capacitance are well established in design flows today, but the methodology for capturing the correct switching activities is currently more of an art than a science.

Power simulation problem

Traditionally, switching activity generation is seen as a by-product of logic simulation (see Figure 1). However, there is a fundamental difference between a logic simulation for functional verification, and for the purpose of power analysis and optimization. Functional simulations are designed to cover the "correctness" of the design and to test the corner cases for operational integrity of the chip.

Figure 1 — Basic power analysis methodology

A typical functional verification strategy is to sequentially test each of the functional blocks in a design in turn, while keeping the other blocks disabled. This works well for maximizing functional coverage and makes it easy to debug which functional unit is responsible for a particular functional error, but produces a switching activity which is unlike any real-world use case for the design. Most of the chip is disabled most of the time, which leads to a significant underestimation of the average-case power dissipation. Conversely, other approaches, such as using test vectors produced by Automatic Test Pattern Generation (ATPG) tools, result in unrealistically high power numbers when compared to real-world use of the design. This is because ATPG effectively tries to generate vectors which toggle the maximum number of nodes with a minimum number of clock cycles, which is not a real-world scenario.

There are also situations where a designer is focused on testing a particular piece of critical functionality in a block, and that block is simulated more extensively than the other functional units to make sure it works, even though this critical functionally may only be used relatively infrequently in the field. Consequently, a very high switching activity shows up for that block. In normal operational mode, however, that block may well be inactive, and other blocks may dominate the power consumption.

The examples above show that design teams need to think carefully about where their activity information is coming from when performing power analysis and optimization. Some sources will lead to underestimating the power in the circuit, and some will overestimate it. In either case, using inaccurate activity has the potential to cause power optimization tools to concentrate on parts of the design that do not need power optimization, and miss the areas where power optimization could yield significant benefits.

For accurate power analysis and optimization, it is critical to use logic simulations that are designed to capture the desired real world usage of the end silicon, be that average case, peak, or burst. Creating such testbenches is a non-trivial and time-consuming task. Designers have to spend additional time putting together a number of scenarios during simulation that reflect how the device will really be used in the field.

In practice, it is often difficult to justify the resource necessary to compile such simulations prior to tapeout, since design managers are under strong pressure to use any available additional time and resources to perform additional functional testing, or to simply tape out the design sooner. Furthermore, even if the resource can be made available, runtime constraints typically prevent such simulations from exercising more than just a few fractions of a second of real world usage of the design.

Statistical activity methods

As power becomes increasingly critical, design teams are ultimately facing the problem that they need something for nothing: credible activity estimation with minimal resource and time overhead. One approach to resolving this problem is to exploit statistical methods to "predict" net activities instead of using a detailed power simulation to compute them.

Statistical methods are based on solving a set of inter-related mathematical equations that express the switching probability of each logic gate output as a function of the switching probabilities at other logic gate outputs in the circuit. For example, a simple statistical activity method might define the switching activity on a gate output purely in terms of the switching activity of the inputs to that gate, as shown in Figure 2.

Figure 2 — Traditional statistical activity propagation approach

Statistical activity methods are generally much faster than logic simulation, but are often unable to give a credible estimate of the true behavior of a design. An extreme case would be the trivial approach of assuming all gate outputs have the same fixed activity rate (such as 1 in 10 clock cycles), which results in a very fast power estimation engine, but also one which is unlikely to correlate well with the real world usage of the design.