About that high quiescent current

We talked more about the application and he told me that in standby mode the input signal was removed so the output should be zero he reasoned. That was my clue. With the input pin open there is no path for input bias current and the input voltage drifts to the rail.

The topology of a rail-to-rail output stage, realized with bipolar transistors, shows how the quiescent current can go quite high if the output is driven to an extreme negative voltage. To obtain a negative output voltage it is necessary to turn Q3 on. The current through Q3 is controlled by the limiting circuit but the IC designer has a fine line to balance. Allow enough current so the output swing specs are met but do not allow too much. Quiescent current reaching ten times the rated maximum at saturation is an extreme event.

In the case of my caller, the cure was quite simple. A resistance from the input pin to ground allowed for a bias current path and the part never was set to an extreme output. In some applications more extensive cures need to be applied to ensure that the output is not driven to an extreme.

Thanks for readingComments Please. klein_bill@ti.com And be sure to copy, you-know, sohr@cmp.com

*Applications guru Bill Klein in host the Analog eLab web seminars sponsored by Texas Instruments and CMP Media.