PROPOSED STRATEGY

The inductor current, which cannot be determined completely through the capacitor voltage ripple, is independently sensed and regulated through a separate hysteretic loop, containing the main switch S_M. The average inductor current I_L is raised above the minimum value required to support load current I_O. Starting with a standard boost converter, an additional auxiliary switch S_A is added across the inductor L. When the switch S_A is open, the excess inductor current (above the minimum value) tends to charge the capacitor C beyond the desired output voltage. This overcharge is sensed and prevented by comparator Q₁, which turns on switch S_A and shorts inductor L. Therefore, the inductor current freewheels, shutting off diode D and letting the capacitor voltage discharge. Switch S_A is turned back off when the sensed capacitor voltage V_S discharges below reference V_REF. The hysteretic problem is thus defined to regulate the output voltage to a desired value between (V_IN - V_Diode), which is its equilibrium value with switch S_A closed, and I_D(V_OUT/I_O), which is its equilibrium value with switch SA open. This regulation is performed by controlling the duty cycle D_A of switch S_A. At the appropriate duty cycle D_A, the diode current I_D, averaged over a switching cycle of S_A, equals the load current I_O, and average V_OUT is stabilized to equal V_REF. Switch S_A switches asynchronously to switch S_M at a much lower switching frequency.

The additional power loss due to higher inductor current is kept low by maintaining the inductor current only 5% above the minimum required value (I_{L_Min}). A representative inductor current reference (V_IREF) is derived from duty cycle D_A, by means of a charge-pump-based duty-cycle-to-voltage demodulator shown in Fig. 1b. Capacitor C₁ is charged and discharged by complementarily switching current sources I₁ and I₂, which are gated by the controlling signal of switch S_A. The average capacitor current equals zero and the voltage VIREF stabilizes when the total charge injected into the capacitor by I1 during the off time of switch S_A balances the total charge removed by I₂ during the on time of switch S_A. By setting I₂ to be 19 times larger than I₁, V_IREF reaches steady state only when the off time of S_A (I₁ charging C₁) is 19 times greater than the on time of S_A (I₂ discharging C₁), i.e., duty cycle D_A is 5%. If the steady-state duty cycle D_A is increased, the load transient response of the converter improves at the cost of reduced power efficiency. With duty-cycle D_A chosen as 5%, the efficiency of the proposed converter is degraded by approximately 2% as compared to a standard boost converter, at a load of 0.5A [3].

A fast, large increase in load current causes the output voltage to drop sharply because the inductor current is not high enough to support the increased load. Comparator Q₃ senses this voltage drop and turns on switch MPC1, thereby raising the inductor current reference to the level that is required to support the maximum designed load current. The inductor current rises, in a single cycle of switch S_M, to the new reference and then charges the output capacitor, in a single cycle of switch S_A, to V_REF. Once the output voltage reaches V_REF, switch M₁ turns off and the inductor current reference V_IREF decays until the duty-cycle D_A reaches the 5% limit. The comparator is designed with an asymmetrical hysteresis, being narrower than that of Q₂ on the positive side and wider than that of Q₂ on the negative side.

Simulated waveforms in steady state for the operating conditions tabulated in Table 1, are shown in Fig. 2a. The output voltage V_OUT and inductor current I_L are seen to have two ripples viz. a high frequency ripple corresponding to the switching of switch S_M and a larger, low frequency ripple corresponding to switching of switch S_A. Transient waveforms for a step load change from 0.3 to 0.6 A are shown in Fig. 2b. Simulations show that stable converter operation is obtained for capacitor (C) and ESR ranges of 3-200μF and 0-35mΩ respectively, under inductor (L) variation of 1-30μH at 1 A load. The acceptable ESR range is extended further at lower load levels.

Table 1. Simulation parameters and conditions

Figure 2a. Simulated waveforms in a steady state for the proposed circuit at V_IN=1.5V, I_O=0.3A, V_OUT=3.3V, f_SW (SA) =5kHz, f_SW(S_M) =1.6MHz with three switching cycles of switch S_A showing V_OUT, I_L, V_IREF, and V_GA

Figure 2b. Step load from 0.3 to 0.6A, V_IN=1.5V, V_OUT = 3.3V showing I_L and V_OUT.

FUTURE WORK

The proposed technique provides stable performance and single-step transient response for a wide range of filter L-C values without the use of any external compensation circuit, thus suitable for integration. However, three main drawbacks are evident. Firstly, the output voltage has a somewhat large steady-state ripple at a low frequency, which may lie in the audible range; secondly, the additional switch S_A, which carries current in steady state, can be quite large in size, and, thirdly, the additional inductor current leads to a reduction in power efficiency. The future work in this research involves addressing all these concerns while maintaining the aforementioned benefits. Currently, a prototype board is being built to verify the simulations through experimental results and to determine the L-C compliance of the proposed circuit.

References
[1] G.A. Rincn-Mora, "Self-Oscillating DC-DC converters: From the Ground up," IEEE Power Electronics Specialists Conference Tutorial, 2001.
[2] R. Miftakhutdinov, "Analysis of synchronous buck converter with hysteretic controller at high slew-rate load current transients," Proceedings of High Frequency Power Conversion Conference, 1999, pp. 55-69.
[3] N. Keskar and G.A. Rincn-Mora, "Self-Stabilizing, hysteretic, boost DC-DC converter," The 30th Annual Conference of the IEEE Industrial Electronics Society, IECON 2004, Nov 2004, TA3-4.

For additional details, questions, and/or comments on this article, please contact us, the Georgia Tech Analog and Power IC Design Lab, at gtap@ece.gatech.edu.

More information about our research can be found at www.rincon-mora.com/research