Chip-scale packaging comes of age for power devices

The benefits of chip-scale packages are fairly obvious. In space-constrained, very dense designs, every bit of board space is precious. Chip-scale packaging, which eliminates the extra space along the sides of conventional device packages devoted to wire leads, saves valuable board space for other critical on-board functionality. With a chip-scale package, the silicon die is attached directly to the circuit board by solder bumps underneath the die.

But everything comes with trade-offs and "the rap" on chip-scale packaging is that it creates additional assembly and manufacturing difficulties and raises some board-level reliability issues. In certain applications and types of devices, the benefits of space-saving chip-scale packages have been enough to overcome any trade-offs. Now, from the industry's more than ten years of experience with bumped packages like ball grid arrays (BGA) and flip chips, chip-scale has arrived for a wide variety of power devices.

Driven by demand

One only needs to pick-up a smartphone, personal digital assistant (PDA) or a slim laptop computer to realize that space-saving packaging is very desirable for many popular applications. In portable or hand-held systems, board space "real estate" is highly-valued. If most system designers could, they would probably devote most of the board space to functionality because that's what sets their products apart in the marketplace. While power devices are essential to enabling that functionality, power is not the system's primary function and board space allocated to it is scrutinized conspicuously.

Space-saving concerns are also intruding on more traditional applications where the PCB footprint of many devices has not been a major issue. For example, a new compact-type of desktop personal computer is growing in popularity. Called a portable desktop, the system enclosure is small and unobtrusive and provides "a clean-and-uncluttered" desktop. Sometimes the computer is so small that it can be hidden inside the monitor's base.

In the future, the trend toward miniaturization will continue to touch a wider range of applications throughout the computer, communications and electronics industry. So in general, the increasing demands for smaller chip-scale packaging in power devices as well as other types of semiconductors will continue.

The packaging cycle

New, innovative types of packages typically follow some type of adoption trajectory. For example, when surface-mount packaging was introduced more than 20 years ago there was industry "resistance." The performance of surface-mount packaging had to be fully-evaluated and analyzed before adoption could be contemplated. New handling and assembly equipment had to be installed and brought up-to-speed. And even after these hurdles had been crossed, only the applications that most needed the advantages of surface-mount packaging embraced the new packaging in a big way. As time went by and surface-mount proved its worth, it was adopted throughout the industry in practically every type of application and for most types of semiconductor devices.

Similarly for power devices, when leadless packages like the QFN [quad flat no-leads package] were introduced several years ago. They were accepted in many applications. However, QFN packages also met with some resistance since a new package means changes in manufacturing. The same is happening with chip-scale power devices. Once manufacturers realize the benefits associated with chip-scale packaging, the adoption cycle will accelerate.