Deploying a new system bus always entails some risk, particularly from narrower component offerings, but improved system performance, system stability, computer performance, software design and future scalability pay the dividends the designer seeks. Sufficient backing of the Simple Serial Transport by system and component vendors looks promising after a short enabling period that began in 2005.

The Simple Serial Transport ensures predictability where each bit maintains guaranteed timing. Such a guarantee is not to be dismissed or passed over quickly. The nature of bus stretching is unsettling in itself. However, examples of predictable self-clocked data are common. Manchester-encoded data represents one general type of predictable clock-embedded timing. Figure 1 shows a common type of Manchester-encoded data. The clock is extracted, usually with the help of a digital phase-locked loop.

Figure 1. Manchester-encoded logic 1 and logic 0 bit stream (cit. IEEE 802.4 Standard, 1997)

Strength of the method
Once extracted, data from the "1 0" bit stream in Figure 1 decodes to 01 10. (The bit patterns 01 and 10 represent legally decoded bit patterns from a Manchester encoded signal, patterns with repeating bits, 00 and 11, are illegal patterns. Recognizing legal patterns increases the encoding scheme's reliability. ) Applying design techniques to decode this pattern and recognize the permissible decoded pattern is one of the strengths of this communications method. This encoding scheme has no dc component and does not require a separate clock wire. Such a design is easy and cheap enough to implement on a large ASIC, but may be too costly for small sensors. The Simple Serial Transport provides a less complex way to pass timing reliably between components. Whereas Manchester encoding extracts a clock from a bit pattern, the Simple Serial Transport positions a rising edge at the beginning of every data bit and guarantees a signal transition within the bit's timing frame.

Figure 2. Simple Serial Transport logic 1 and logic 0 bit stream (cit. Analog Devices, Inc. ADT7484A data sheet, June 2006)

There's no free lunch; both Manchester encoding and Simple Serial Transport pay a price to embed a clock in the data signal. For the former, the wire bandwidth is two times larger than the symbol rate and for Simple Serial Transport the wire bandwidth is four times greater than the symbol rate. The intrinsic bandwidth of the traces in modern computer systems is far in excess of the bandwidth Simple Serial Transport communications requires to support symbol rates above 1 Mbps. As the bus migrates to wider usage, other applications could take it between boards or through backplanes. The bus can support differing bandwidths using other features of the bus that allow a flexible symbol rate.

Knowing when the bit begins and ends is a key aspect of the Simple Serial Transport's stability and reliability. The bit pattern design allows for many different decoding methods. Following the Manchester encoding scheme, Simple Serial Transport's 1 0 bit stream is decoded as 1110 1000. The ability to separate legal patterns from illegal patterns establishes a high level of noise immunity by itself. Another method leverages the intrinsic 1 0 as either a ¾ or ¼ bit time of a high signal to a low signal, respectively. This bit frame permits the digital implementer an easy timer-based decoder. Knowing the length of one bit frame, the timer design can sample for a signal transition before and after the half way point of the bit frame. Using ¾ and ¼ ratios in Simple Serial Transport timing allow for plenty of timing margin in this design choice.

Figure 3. Simple Serial Transport low-noise sensitivity

Low noise
The nature of the timing or digital decoding methods permits aggressive signal integrity design to be applied in any IC for a cost-effective and robust link. The application of traditional noise dampening IO structures or filters limits inadvertent or double bit starts. When such a design is required by the specification, the bus automatically raises its robustness by orders of magnitude. The predictable bit frame timing featured by Simple Serial Transport permits digital methods to ignore transient noise spikes that would otherwise disrupt most other methods. The Manchester method, for example can use multiple samples to verify both the bit code and that a transition occurred in the bit stream. Similar techniques apply to Simple Serial Transport input cell design. Once these physical and data link layer techniques combine with communications robustness added in the network layer, a truly reliable bus takes its shape.

It's important to look everywhere a bus can create a noise spike or be susceptible to noise. To verify noise performance, Analog Devices engineers embedded the Simple Serial Transport into traces on an existing Intel computer motherboard. The computer design featured a recent CPU and chipset with a VR10.1 CPU regulator and high-speed DDR memory. Traces carrying Simple Serial Transport signaling routed directly past the memory DIMM slots and CPU voltage regulator. These two areas may be two of the nosiest regions of a computer board. These traces connect to the ADT7484A remote thermal sensor.

Extracting temperature data information across a management bus can be mission critical in systems operating at peak power and efficiency. The performance of Simple Serial Transport compared well to more traditional system management busses. The following data collected the noise upset rate of 1Mbps messages sent while the PC performed various tasks, such as, playing an MPEG movie clip or forcing the CPU to 100 percent utilization through test software. Collecting data over 7 billion bits show that the Simple Serial Transport design attained expected noise immunity results.

Table 1 Simple Serial Transport noise performance results

The Simple Serial Transport can be an excellent vehicle for system management links where a system cannot afford a bus to "hang." The bus design goals of meeting predictable, fast system performance and high noise immunity are key features of the Simple Serial Transport bus. Why does this help? A fast and reliable management bus will enable system designers to reduce message re-try likelihood and use the bus for more time-critical functions. Simply put, the computer can inventory its installed hardware quickly, boot or manage itself efficiently and provide real-time diagnostic information for management consoles.

Obtaining a license
Additional features are described in the specification. To obtain a royalty-free license agreement to the Simple Serial Transport specification, contact Analog Devices by sending an email to sst_licensing@analog.com.

About the author
Dale Stolitzka is a chief systems architect in Analog Devices' Power and Thermal Computing Group. His experience includes computer systems and mixed-signal systems design. He has worked at Analog Devices for eight years; his prior experience includes systems and design positions at National Semiconductor, Maxtor and Raytheon. Dale holds a BS in applied physics and an MEng in materials science from Cornell University. dale.stolitzka@analog.com