The well-known classical capacitor model comprises an ideal capacitive element in series with a resistance and an inductance. The primary purpose of the input capacitor for the typical switchmode supply (Fig. 1) is to provide energy to the power stage (Q1, Q2, L, C_OUT) quickly when Q1 closes and charges L during steady-state operation.

Without the input capacitor, the pulsating current of Q1 would need to be completely supplied by the host source, V_IN, which commonly does not have sufficiently low output impedance. Thus there would be substantial noise on the host voltage source and an increase in the conducted EMI on the board. The input capacitor, C_IN, effectively filters the input current so the current from the host source is approximately an average current.

Figure 2 shows the current flow into the buck supply during the on-state and off-state.

The governing equations are as follows:

Here we assume that the capacitor's equivalent series resistance (ESR) and equivalent series inductance (ESL) result in fast rise and fall times.

A few interesting facts pop out of the equations. Note, for example, that the RMS current will be greatest at 50 percent duty cycle. If we assume the ratio of output current ripple to average current is fairly small, the input ripple current will be directly proportional to average output current. Therefore, a smaller load current means less ripple, and thus less capacitance is required for a given amount of input ripple voltage.

Let's use the equations to determine the appropriate input capacitor for steady-state operation. Typically, designers choose an input capacitor based solely on its RMS current and voltage rating. But let's use equations 1 and 2 to select the capacitor based on a desired input-voltage ripple. In most cases, a variety of different capacitors in parallel are required to minimize the effective ESR and ESL contribution to the ripple, as well as for current sharing to ensure reliable operation.

So now we have a method to simplify the input capacitor selection. To decrease the effect of ESL and ESR, we first select ceramic capacitors to limit the amount of input ripple voltage. Then we select the amount of required bulk input capacitance to minimize deviations in the input voltage should a large load transient occur.

Given the very low ESR and ESL of ceramic capacitors, we derive the following relationships (Fig. 3) based on the buck converter's current flow shown in Fig. 2.

The equations above define the minimum capacitance needed to limit the input ripple voltage to a desired value; usually recommended to be less than 1 percent of the input voltage. At this voltage, we ensure the input ripple current is within an acceptable range for the bulk capacitor. As a result, we significantly increase the capacitor's lifetime. Ceramic capacitors with high quality dielectrics such as X5R or X7R should be used to provide a constant capacitance across temperature and line variations. Since the equation calculates the actual capacitance required and the capacitance of a ceramic is voltage dependent, the capacitor selected should be derated accordingly. Also, the ceramic capacitor must be able to tolerate the RMS current, which can be calculated using equation 4.

Next, we calculate the amount of bulk input capacitance required to ensure a stable input voltage during large load transients (Fig. 4). The input supply is typically incapable of providing the required input current quickly enough for the converter to respond to a fast transient current. The input bulk capacitor provides the energy necessary to source current to the buck supply until the host supply is able to fill the demand. Ceramic capacitors are usually inadequate due to their high cost per farad. Figure 4 shows how to estimate the amount of bulk capacitance. We calculate the input reflected transient current using equation 12, where the efficiency, η, can be estimated by consulting reference designs for the specific control IC.

Equation 14 will approximate the absolute minimum capacitance required based on the estimated series inductance. A reasonable value for stray series inductance due to PCB layout is at least 50 nH. The designer should select the amount of bulk input capacitance with margin since the approximation assumes the host supply is well regulated and neglects the ESR. You should also verify the RMS ripple current using the ripple voltage target chosen when calculating the ceramic capacitance. The bulk capacitance should have low ESR to minimize its voltage drop during the time it supplies current during the transient. The allowable voltage deviation, ΔV, on the input should include consideration for the under-voltage lockout of the control IC.

The table lists a few capacitor types that are usually appropriate for the bulk capacitor. Several of these capacitors in parallel may be required to provide the design capacitance.

To summarize, the input capacitors must be selected with care to ensure the buck converter operates as intended and reliably. In some cases the host supply may be able to provide sufficient current to the converter or several co-located buck supplies may be able to share input capacitance, but this is at the discretion of the designer. For the buck type, point-of- load converter, it's typically best to start with ceramic capacitors to limit the input voltage ripple and in turn limit the input current ripple. Ceramic capacitors are most appropriate due to their low ESR and ESL, and also their high ripple current survivability. Add more bulk capacitance as necessary to prevent droop on the input supply during large load transients.

References
[1] Lynch, Brian and Kurt Hesse, Under the Hood of Low-Voltage DC/DC Converters, TI Technical Brief, 2006.

[2] Input and Output Filters for Z-OneTM POL Converters, Power-One Application Note, 2006. Rev 1.1

[3] Mathcad Calculates Input Capacitor for Step Down Buck Regulator, Maxim Application Note 842, 2001.

[4] Arrigo, Jason, Input and Output Capacitor Selection, Application Report, TI Literature No. SLTA055, 2006.

About the author
Chris Cooper is a field applications engineer in the Ottawa, Canada branch of Avnet Electronics Marketing. His primary focus is on providing technical support for analog and power management applications. Prior to joining Avnet, he focused on circuit board design for biomedical devices and telecom systems.