Overview
Consider a 3-amp switching regulator that takes 24 volts down to 3.3 volts. Now, a 10-watt regulator doesn't initially appear too difficult, and the designer might be tempted to launch right into the building phase.

But let's see what's actually involved by applying some design software, such as National's Webench. If we enter the aforementioned requirements, Webench proposes among other ICs the LM25576 from the company's "Simpler Switcher" series, a 42-volt input device that includes a 3-amp FET. It's packaged in a TSSOP-20 with thermal pad.

Webench options include optimizing the design either for size or for efficiency. The choice really is an "either/or."That is, high efficiency requires a low switching frequency (to keep the switching losses down in the FET). Thus, the design requires large value inductors and capacitors, which take up more board space. Webench shows your options as follows:

As an aside, note that the efficiency peaks at 84 percent and that the best efficiency is achieved when the input-to-output voltage difference is low. In this example, the input-to-output ratio is greater than seven. Often, the stage-to-stage ratio is reduced using two stages, but the resulting efficiency over two regulators will not be better.

To continue, we choose the highest switching frequency having the smallest board space. The high switching frequency will most likely generate problems with the layout. Webench generates a circuit diagram with all passive and active components.

The circuit
The simplified circuit diagram shown below is of great help in understanding the basic situation. Let's take a look into the current paths: Mark the ones in red that apply to the FET in its ON state, and mark the ones for the FET in its OFF state with a green pencil. We observe two different scenarios: Areas of two colors and areas with only one color. We must pay special attention to the latter condition, because there the current alternates between zero and full value. Those are the areas with a high di/dt.

Alternating currents with high di/dt generate a significant magnetic field around the PCB traces, and that's a major source for interference in other parts of the circuit and even other circuits on the same or adjacent boards. Common current paths are less critical assuming it's not an alternating current, and thus the effects of di/dt will be much less. On the other hand, those areas carry a higher load over time. In this example, common paths exists from the diode's cathode to the output and from output ground to the anode of the diode. The output capacitor shows extremly high di/dt as the capacitor charges and discharges. The traces to and from the output capacitor have to fulfill two conditions: They need to be wide because of the high current, and as short as possible to minimize di/dt effects.

In practice, the designer wouldn't implement a so-called traditional layout with traces running from V_out and ground to the capacitor. Those traces will be the ones carrying high alternating currents. A much better way to connect the output and ground directly to the terminals of the capacitor. Thus, alternating changing currents are only found at the capacitor. The remaining traces to the capacitor will now carry an almost constant current flow, and any problems with di/dt will be solved.

Ground is another mystery that is quite often misunderstood. Simply placing a groundplane in "level 2" and connecting all ground connections to it will not show good results.

Let's take at a look why. Our design example has currents of up to 3 amps that have to flow through ground back to the source (a 24-volt car battery or a 24-volt power supply). The diode, COUT, CIN and the load have high current at their ground connections. The ground connection of the switching regulator carries little current. The same is true for the ground reference of the resistive divider. If all the above ground pins are connected to a ground plane we would get ground bouncing. Although small, the sensitive points in the circuit (such as the resistive divider that derives feedback voltage) will not see a stable reference ground. Thus overall regulation accuracy will suffer greatly. Actually, we could even get ringing from the source hidden within the groundplane on level 2, and that's very hard to locate.

In addition the high-current connections would have to use vias to the groundplane, another source of interference and noise. A much better solution uses the ground connection of CIN as a star point for all high current ground traces on the input as well as on the output side of the circuit. This star point is connected to the groundplane, as well as the two low current ground connections (IC and divider).

Now the groundplane will be clean: No high current, no bouncing. All high-current grounds are star connected to CIN ground. All the designer has to do is make the ground traces (all on the top level of the board) as wide and short as possible. In that context, saving copper per se has never shown good results.

Impedance of the nodes
The nodes to check are the high-impedance ones, as they can easily catch interference.

The most critical node is the feedback pin of the IC, which receives its signal from the resistive divider. The FB pin is the input of an amplifier (as with the LM25576) or a comparator (as is the case with hysteretic regulators). In both cases the FB point has quite high impedance. Accordingly, the resistive divider should be located right at the FB pin, with a short trace from the center of the divider to FB. The trace from the output to the divider is low impedance and can be routed to the divider over some longer trace. The length of this trace is not critical, but the routing is.

Other nodes, on the other hand, aren't so critical. So don't worry about the switching node, diode, COUT, the VIN pin of the switcher IC, or CIN.

Routing of traces
Routing makes a difference for the resistive divider. This trace goes from COUT to the divider and its ground back to COUT. We have to make sure that this loop does not form an open area. Open areas can act like receiving antennas. If we can make sure that the groundplane below the trace is undisturbed, then the area made up by the trace and ground below it and the distance between level 1 and level 2 should be clean from interference. Now it becomes clear why ground should not be on level 4. The distance would be significantly increased.

Alternatively the ground connection of the resistive divider could be routed on level 1, with both traces in parallel and as close together as possible to keep the area small. These observations apply to all traces that carry signals: Sensor connections, outputs of amplifiers, inputs of ADCs or audio amplifiers. Every analog signal should be treated in a way to reduce the capability to pick up any noise.

Minimizing open board areas whenever possible also holds true for low-impedance traces; we have in this case a source ("antenna") for potentially transmitting interfering signals to other sections of the board or device. Again, smaller is better when it comes to open board areas.

Two other critical traces include the one from the switching output of the IC to the node of the diode and inductor; and the trace from the diode to this node. Both traces carry high di/dt: either the switch is ON or the diode carries current, and so the traces need to be as wide and as short as possible. The trace from this node to the inductor, and from the inductor to COUT, are less critical. In this case, the inductor current is relatively constant and changes slowly. All we have to do is make sure it's a low impedance point to minimize voltage drop.

Practical layout
Let's take a look into a good layout (below). The main component is a controller in an MSOP-8 package, used in conjunction with an external FET.

Take a look in the area of CIN. Notice that the ground point of this capacitor is directly connected to the anode of the diode. You cannot make the trace in "power ground" much shorter! The FET [SW] could be moved a few millimeters up to shorten the cathode-inductor-FET trace.

The area of COUT is not visible. But we can observe that the resistive divider (FB1- FB2) is very close to the IC. FB2 is grounded to a separate ground plane, and so is the ground pin of the IC. This "signal" ground is connected to the ground plane using three vias, the same as for the "power" ground connected at the GND pin of the board. This way, "signal" ground can not see any bouncing that occurs on the "power" ground.

If you apply a few simple rules—only some of them have been discussed here—the board layout will be virtually free of trouble. Spend the time to really think about board layout before you lay it out— it'll save you time later in trying to cure some obscure behavior in your switching power supply.