Critical layout tips for fast switchers

Overview
Consider a 3-amp switching regulator that takes 24 volts down to 3.3 volts. Now, a 10-watt regulator doesn't initially appear too difficult, and the designer might be tempted to launch right into the building phase.

But let's see what's actually involved by applying some design software, such as National's Webench. If we enter the aforementioned requirements, Webench proposes among other ICs the LM25576 from the company's "Simpler Switcher" series, a 42-volt input device that includes a 3-amp FET. It's packaged in a TSSOP-20 with thermal pad.

Webench options include optimizing the design either for size or for efficiency. The choice really is an "either/or."That is, high efficiency requires a low switching frequency (to keep the switching losses down in the FET). Thus, the design requires large value inductors and capacitors, which take up more board space. Webench shows your options as follows:

As an aside, note that the efficiency peaks at 84 percent and that the best efficiency is achieved when the input-to-output voltage difference is low. In this example, the input-to-output ratio is greater than seven. Often, the stage-to-stage ratio is reduced using two stages, but the resulting efficiency over two regulators will not be better.

To continue, we choose the highest switching frequency having the smallest board space. The high switching frequency will most likely generate problems with the layout. Webench generates a circuit diagram with all passive and active components.

The circuit
The simplified circuit diagram shown below is of great help in understanding the basic situation. Let's take a look into the current paths: Mark the ones in red that apply to the FET in its ON state, and mark the ones for the FET in its OFF state with a green pencil. We observe two different scenarios: Areas of two colors and areas with only one color. We must pay special attention to the latter condition, because there the current alternates between zero and full value. Those are the areas with a high di/dt.

Alternating currents with high di/dt generate a significant magnetic field around the PCB traces, and that's a major source for interference in other parts of the circuit and even other circuits on the same or adjacent boards. Common current paths are less critical assuming it's not an alternating current, and thus the effects of di/dt will be much less. On the other hand, those areas carry a higher load over time. In this example, common paths exists from the diode's cathode to the output and from output ground to the anode of the diode. The output capacitor shows extremly high di/dt as the capacitor charges and discharges. The traces to and from the output capacitor have to fulfill two conditions: They need to be wide because of the high current, and as short as possible to minimize di/dt effects.

In practice, the designer wouldn't implement a so-called traditional layout with traces running from V_out and ground to the capacitor. Those traces will be the ones carrying high alternating currents. A much better way to connect the output and ground directly to the terminals of the capacitor. Thus, alternating changing currents are only found at the capacitor. The remaining traces to the capacitor will now carry an almost constant current flow, and any problems with di/dt will be solved.

Ground is another mystery that is quite often misunderstood. Simply placing a groundplane in "level 2" and connecting all ground connections to it will not show good results.