Power considerations in designing with 90 nm FPGAs

In order to compete for sockets in many prime target applications, vendors must find ways to enable the designer to reduce FPGA power consumption in the entire system. Excessive power is expensive in many ways; it creates the need for special design and operational considerations – requiring everything from heat sinks to fans to sophisticated heat exchangers. Even the cost of larger power supplies as well as energy charges must be taken into consideration.

Managing power within the system budget is essential not only to reduce capital and operational expenditure, but often to maintain reliability as well. As their junction temperatures rise, transistors consume more power, thereby further increasing the temperature of the device. Left unchecked, this positive feedback loop can lead to thermal runaway (see also the Xilinx whitepaper Static Power and the Impact of Temperature).

Case study: storage-server power issues
Indicative of the side effects of system-level integration, today's data centers are facing a power management crisis. Having discovered that they could greatly increase the number of servers in the data center by replacing rack-mounted server farms with a very large number of blades crammed into a 19-inch server rack, data center managers soon realized they had also created the beginnings of a full-scale power glut. Due in large part to clever blade engineering, specialized low-power processors, and carefully designed airflow, power consumption figures for the average data center are expected to drive data center power costs through the roof. Thus, finding ways to cut power consumption is a top priority.

To quantify these power consumption trends, consider a typical 50,000 sq. ft. data center today with rack-mounted servers that average 40W/sq.ft at a cost (cooling and energy) of about $20M per year. At the present rate of growth in capacity, if the data center were to stay with rack-mounted servers, the number would hit 500W/sq. ft. in the near future, raising the annual power cost to $250M. Besides being too costly from the standpoint of power versus capacity, such an environment would be nearly impossible to cool, making reliability a veritable nightmare.

By moving to the blade, the IT manager can increase server capacity by an order of magnitude while keeping power consumption within reason. Nonetheless, finding a way to decrease power consumption on these blade servers goes right to the bottom line. A typical data center that uses blade servers can expect numbers similar to those below:

• Data Center Blade Servers
  • 1 FPGA per blade
  • 14 blades per shelf
  • 10 shelves per rack
• Power budgets
  • Blade = 143W
  • Shelf = 2000W
  • Rack = 20KW, 80W/sq. ft

As we see, with one FPGA on every blade and 140 blades per rack, selecting the right FPGA could save up to 560W per rack, which equates to as much as $1.2M per year in the typical 50,000 sq. ft. data center.

Static versus dynamic power consumption
There are two major components to power consumption in FPGAs: static power and dynamic power. Static power consumption occurs as a result of leakage current across the gate oxide in the transistors that the FPGA comprises. With each new process generation, as transistors get smaller and the gate oxide becomes thinner, their leakage current increases.

Dynamic power, on the other hand, is the power required to charge and discharge the capacitive loads within the device. It is highly dependant on toggle rate, frequency, voltage, and capacitance. Thus, as the core voltage and total capacitance decrease with each new process shrink, it tends to lower dynamic power. Dynamic power increases, however, at higher operating frequencies and with higher toggle rates.

The well-known formula for dynamic power that applies here is:

   P = kCV²f

or…

   Dynamic Power = Capacitance × Voltage² × Frequency

Historically, dynamic power has always been the larger contributor to power consumption. At 90nm, however, we are seeing a major inflection point where static power is overtaking dynamic power as the key issue. According to the 2003 International Technology Roadmap for Semiconductors (ITRS) projections, static power is increasing exponentially at every process node, making imperative the development of innovative process technologies to stem this troublesome trend (see also the Xilinx whitepaper Power versus Performance at 90nm).

Static power reduction
Reducing static power in FPGAs is a matter of selecting the right vendor and the right FPGA. There is virtually nothing one can do from a user design standpoint that will accomplish much in the way of reducing static power. As we continue to push semiconductor performance by creating smaller, faster transistors, we must rely on innovative process technologies to stem the growth of static power consumption.

One interesting point is that, unlike ASICs, ASSPs, and microprocessors, FPGAs do not need all of their transistors to switch at maximum speed. A substantial number of transistors make up the configuration memory cells used to configure logic, along with the pass transistors used to implement the programmable interconnect routing. Configuration memory cells do not need to be fast, while programmable interconnect transistors only need to be fast from source to drain (and not under gate control).

FPGAs can take advantage of the abundance of these particular types of transistors to incorporate a new process approach called "triple-oxide technology" that dramatically reduces static power consumption. For example, Figure 1 shows that, by employing triple-oxide technology, some 90nm FPGAs reduce static power by 50% versus their 130nm predecessors.

What is Triple-Oxide Technology?
For many years, semiconductor vendors have used two gate-oxide thicknesses: a standard thin layer used for the vast majority of transistors and a thick oxide layer for I/O drivers. Triple-oxide refers to the use of a third thickness of gate oxide in making the configuration memory cells and pass transistors.

The use of triple-oxide technology dramatically reduces the static power component, but increasing the gate oxide thickness has a detrimental effect on performance and has to be used selectively. Similarly, threshold voltage also impacts leakage and performance. Reducing power must be part of product planning and IC design engineers need to carefully balance various parameters. As shown in Table 1, the careful management of various process parameters enables low static power without impacting performance.

Amazingly, a comparison of relatively equivalent devices from both the 130-nm and 90-nm nodes reveals 50 percent less static power consumed by deploying triple-oxide technology.

As the users' only intervention with respect to static power is in device choice, a key recommendation is to pick the FPGA that provides the right amount of resources (not more!). Any extra resources unused in your design will still consume static power. Consider the number of devices available in the FPGA family and availability of varying resource ratios (memory, FIFOs, I/O, clocks, DSP, processors, transceivers) with respect to logic density. For example, as a DSP designer, you should be able to choose an FPGA with 120 DSP functions and 10,000 logic cells for control logic instead of being forced to pick a 90,000 logic cells for 120 DSP functions.

Dynamic Power Reduction
Unlike static power, dynamic power consumption is predominantly design-dependent, being affected by factors such as system performance (switching frequency), power supply voltage levels, design density (number of interconnects), design activity (the percentage of interconnects switching), output loading and clock management. Having made the appropriate architectural-level choices on the first two factors, one must make informed decisions at every step in the design process to minimize the contributions to dynamic power arising from the remaining factors (among others).

Design Density: Wherever possible, use hard-coded compact IP cores and dedicated logic rather than general-purpose slice logic. Not only does dedicated logic have higher performance, but it requires less density and therefore consumes less power for the same given operation. Consider the types and quantity of dedicated logic when evaluating your device options.

Design Activity: Always use clock-enables to activate registers only when the data on the bus is relevant to them. It is best to enable the data early in the path to prevent unnecessary logic transitions, as shown in Figure 2. The waveforms in red indicate the original design; the ones in green indicate the modified design.

When designing state machines, pay attention to state machine encoding that impacts toggle rate. One-hot or gray codes will minimize the number of logic transitions (frequency) for when moving from state to another. Identify common state transitions and select values appropriately while eliminating redundant states.

Output Loading Selecting an appropriate I/O standard can save power, but this is – of course – subject to your design requirements. Whenever possible, choose lower drive strength and lower voltage standards. Pay careful attention to the default standby state of I/Os; for example, some I/O standards (such as GTL/+) require a pull-up, which means you can save the static power through the termination resistor by choosing the default state to be high instead of low.

Clock Management Choose your clocks wisely; if parts of the design do not need to run at high frequency, don't force them to. Also, if portions of the design go inactive, use a global clock buffer to disable those portions of the clock tree from toggling. This achieves the same purpose as using clock enables, but consumes lower power by preventing even the clock tree from toggling.

For more power saving design techniques, refer to the design suggestions from senior applications engineer Arthur Yang (you can find these suggestions at www.xilinx.com/xcell).

Conclusion
Reducing power in FPGA designs is a matter of making the right choices from the very beginning at the system architecture level and the FPGA block design level. Minimizing static power consumption requires choosing the right device from the right vendor. Eliminating excessive consumption of dynamic power requires making informed and intelligent design decisions from the concept phase through to platform integration. In support of the latter, a Platform Design methodology is required that provides power estimation tools in two steps: a pre-implementation tool for system architects and a post-implementation tool for FPGA designers.

The pre-implementation tools provide power estimation based on estimates of resource usage, clock frequencies, and toggle rates. With this, you can get a power assessment before any design is completed.

The post-implementation tool analyzes the actual device usage and, in conjunction with actual post-fit simulation data, delivers accurate power data. In the future, designers will be able to impose power constraints along with placement and performance constraints in FPGA software so as to optimize a design for power.

About the author
Anil Telikepalli is Senior Manager, Virtex Solutions, Xilinx, Inc Anil holds an MS in Electrical Engineering (VLSI Design) from the University of Kentucky, Lexington, USA, and a BE in Electrical Engineering from Osmania University, Hyderabad, India. He has worked in various positions in design and applications and holds a patent in advanced multiplier architecture for programmable devices. He is currently responsible for the marketing of advanced FPGA products and solutions at Xilinx.