Tip of the Week: Maximize processor energy savings in media-intensive mobile devices with adaptive voltage scaling

With the wave of high data rate infrastructure expanding across the globe, and the media-intensive devices now available to consumers, feature-rich handsets will be used almost continuously while relying on battery capacity similar to that of a voice-centric device. Imagine all the activities users do on their device currently such as download/share/listen to music, download/share photos, browse the internet, play games and navigate their way to the movie theatres, restaurants and many more. It is becoming a 24-7 lifestyle that requires extended device run-time.

While user experience is important to end users, network operators and content owners also depend on these new media-intensive features, and their extended use, for their revenue. Limited battery life can mean limited revenue as well.

Power conversion efficiency is today already over 90%, and any improvement has only minor impact overall. Therefore it has become necessary to use new techniques to manage energy at the system level. Processors where frequency is scaled based on actual need combined with power management that scales down voltage with frequency, achieve significant reductions in energy consumption, and corresponding increases in run-time.

Voltage Scaling
The concept of voltage scaling and energy savings can be understood by looking at the energy consumption equation of digital systems: E = {(CV_{DD²f) + (VDDILEAK)}t, where the dynamic terms include C (circuit capacitance), VDD (supply voltage), and f (clock frequency); and the static term is dominated by the I (leakage current) of the digital gates. It is readily seen why a common energy saving technique employed in digital circuits involves scaling down the frequency (f) and voltage (VDD) of the processing engine to reduce energy expenditure. Two common voltage scaling techniques are Dynamic Voltage Scaling (DVS) and Adaptive Voltage Scaling (AVS). The energy savings via DVS and AVS can be seen in Figure 1.}

Figure 1. Energy savings via DVS and AVS compared to fixed voltage operation

What are DVS and AVS?
DVS is an open-loop approach that adjusts the voltage and frequency in pre-characterized parings or with a voltage vs. frequency look-up table. These voltages need to be high enough to maintain functionality over all parts and temperatures. While this open-loop approach yields a reasonable amount of energy savings, it cannot realize all the energy savings possible.

AVS is a close-looped approach that reduces the supply voltage to the minimum possible while still allowing tasks to be completed in time. While DVS regulates the supply voltage to a pre-characterized value that is fixed and ignores process, temperature, and power supply variation, AVS actually takes all these factors into account while determining the optimal supply voltage level, guaranteeing minimum energy consumption.

How AVS works
AVS is a system-level solution that reduces the energy consumption of digital System-on-Chip (SoC) solutions by allowing independent and automatic control of the supply voltage of each of the separate processing engines in the SoC. The technology embeds a synthesizable Advanced Microcontroller Bus Architecture (AMBA)-compliant core, the Advanced Power Controller (APC) into the SoC, shown in Figure 2.

Figure 2. AVS Implementation

The APC enables the system to implement either dynamic voltage scaling or full adaptive voltage scaling on the target SoC. The APC ensures that the supply voltage, and therefore the energy consumed in digital logic, is minimized for the current SoC clock frequency through close interaction with the power delivery system, minimizing demands on the power source while providing peak efficiency.

The APC interfaces to the rest of the system using three interfaces: AMBA-compliant host interface, Clock Management Unit (CMU) interface, and the open standard PowerWise Interface (PWI). The host interface is used to control and configure the APC2 while the CMU interface is used to coordinate voltage and frequency changes.

PWI is a simple and fast (up to 15MHz), 2 pin serial interface specifically designed to meet the needs of AVS and DVS while offering extensive programming options for versatile applications. The latest PWI 2.0 standard supports multiple SoCs and peripheral devices on the same bus. The PWI interface is used to communicate power management information to external Energy Management Units (EMU) or to control other peripheral devices.

Conclusion
With more media content available and high-speed data rates emerging, processing at high speed in a media-centric handset while conserving every drop of energy for improved battery life is challenging. Sophisticated power management techniques such as AVS can significantly reduce energy consumption in digital processing, hence extending device run-time and enhancing user experience. By not having to charge the battery every few hours, these advanced power savings allow us to talk longer, get more games played, or have extended video time available. These advances enable us to be more mobile.

About the Author
Joy Taylor has been with National Semiconductor for four years as applications and marketing engineer focused on power management products for portable applications. She has a BSEE from San Jose State University. She can be reached at: joy.taylor@nsc.com