An engineers guide to FRAM

Why use FRAM and not EEPROM for this data? All of this data must be stored upon power fail. The traditional EEPROM solution required a significant amount of capacitance to maintain power on the EEPROM and MCU after the main power supply fails. FRAM eliminates the need for this capacitance, saving cost and space. Figure 2 compares the amounts of data that can be stored by FRAM and EEPROM on power fail.

To see a bigger version of this graphic click here.

Figure 2 demonstrates a theoretical limit. In reality, the limitation is the microcontroller and the power fail circuit. The power fail circuit sets the amount of time the microcontroller has to store data. The earlier the power fail can be detected, the more time you have to store data, but this places greater demands on the voltage regulator to ensure that there are no dips in Vdd that could be interpreted as a power fail.

If your microcontroller can work at a lower voltage, you have a longer period in which to capture data. In figure 2, it is assumed that the power fail circuit stops the microcontroller working at 2.8V. If it could continue down to the lower Vdd limit of the FRAM (Vdd = 2V), you would have much longer to save data (70 mS in the example shown).

You should also consider how fast the microcontroller can collect data and write it. In the above example, the 50,000 writes occur in 10 mS, i.e. 1 write every 200nS. This data rate is only possible with a parallel interface which consumes a lot of the I/O of the microcontroller. With a fast SPI interface (40MHz) the I/O requirement is significantly reduced and the 10mS interval is enough time to write ~5 kbytes, still probably enough for most systems.

FRAM technology offers an efficient alternative over EEPROM when writing data in applications prone to power failure. The endurance of FRAM is so high and the write speed so fast that you could write data whenever it changes. This means that the data would already be present in the FRAM when the power fails and there is no need to write any data during a power fail situation. This small step has a significant advantage; you don’t need to have a reservoir capacitor in the system that keeps the power alive during power fail.

These reservoir capacitors are necessary when designing with floating gate memory, and they have to supply power to the entire system – EEPROM, microcontroller, and any power fail circuit – so they are often large and need to have a low leakage specification. These demands make the reservoir capacitor physically large and significantly more expensive than normal capacitors.

Figure 3 shows the concept of replacing EEPROM plus capacitor with an FRAM once software has been changed to remove the power-fail storage code and replace it with code to store the changes as they occur. This reduction of overall components lowers product cost and reduces time-to-market (simpler software), while adding immense benefit from FRAM’s unlimited endurance and fast write speed.

The technique of eliminating the power fail bottleneck is used in automotive data recorders where data is collected in the event of a crash. Data is written continuously until an event occurs leaving the FRAM with a record of the seconds leading up to the crash. There is one advantage of eliminating the need to save data on power fail. Most engineers, at some point in their career will have worked on problems associated with data being corrupted on power fail. Writing data when the power is stable is a much safer option than trying to cram all of the data writes into that brief period after a power fail has been detected.