Software designers, especially those who work with embedded applications, are well aware of the importance of low-power designs. The truth is that in most situations software people do not have a clue how their design decisions effect the power consumption in the final product. The detailed reasons for this depend on the specifics of the design system being used but, generally speaking, the software designer is too far removed from the hardware and lacks the analysis and feedback tools that would allow effective optimization for power. This is not the case for other performance characteristics such as execution speed and code size for which measurements are readily available, so it is no surprise that those characteristics get optimized. At Improv, we recognized the need for this information in the design process early on and have developed our methodology such that hardware and software optimization are done as a coordinated process with the requisite measurements and feedback available to the designer. The software (application) engineer is in touch with the consequences of design decisions early and can readily predict not only code size and speed, but also power and die size. We find that when given access to good information, the software designer becomes a key resource in producing solutions that meet all specifications, including low power. Victor Berman Improv Systems

"Design for minimum power" is the mantra of many SoC designers—low power is a consideration from the very start of their chip design. The idea of reducing power consumption of the finished product is pervasive throughout the chip's fabrication, specification, and design processes:

• Silicon foundries usually offer a low-power variation of their baseline digital process.
  
  
• Many cell libraries, silicon cores, and silicon compilers have low-power variants of their basic cell, core, and compiler modules.
  
  
• You have your choice of many EDA tools for designing, analyzing, and verifying block and chip-power usage at various design-abstraction levels. Examples include OSC's ORINOCO at the behavioral level, Sequence's PowerTheatre at RTL, and several tools at the gate level.
  
  
• Designing for minimum chip size (and cost) results in shorter interconnect paths, which also means less dynamic power dissipation.
  
  
• The march to ever-increasing system complexity on the chip through continuing process-node reduction (in other words, shrinking feature sizes on a chip) means less inter-chip communications—thus reducing a major contributor to power usage.

While chip-hardware designs are guided—and sometimes controlled—by a directive to reduce chip power, the same cannot be said for designers of the embedded software that will go on that chip. Designers of embedded software have their own set of guidelines, such as maximizing co-design activities with the hardware designers, minimizing the lines of code needed to meet performance specifications, maximizing the speed of the running software, and minimizing the memory the system needs to support software activities. While reduced memory also has a benefit of reducing power, there is generally not a "design for lower power" edict for the embedded software designer.

Techniques for software design to reduce system power do exist. You can find examples of such techniques in various research and conference papers. Three interesting papers are:

• Low Power Architecture Design and Compilation Techniques for High-Performance Processors
  Presented at Compcon 1994.
  The low-power architecture design paper presents two methods for reducing processor switching activity: Gray code addressing (changing only a single bit between consecutive addresses) and cold scheduling (using traditional performance-driven scheduling with special heuristics to reduce switching activities). The authors found that Gray code reduced address-line-switching activity by 30-50% compared to binary-code addressing, while early results with cold scheduling reducing the processor's control-path switching activity by 20-30%. Lower on-chip switching activity translates to lower power.
  
  
• Efficient Instruction-Level Optimization for Low-Power Embedded Systems
  Presented at ISSS (International Symposium on System Synthesis).
  The paper on instruction-level optimization discusses a technique for developing and validating an instruction-level low-power optimization framework for a given instruction-set architecture. Using this technique, the authors found power savings ranging from 2.7 to 29.2% for a variety of applications run on a 32-bit five-stage pipelined datapath.
  
  
• Improving Memory Energy Using Access Pattern Classification
  Given at ICCAD (International Conference on Computer Aided Design) 2001.
  The memory-energy improvement paper presents a compiler-based strategy that modifies the execution order of loop iterations in array-intensive applications (such as image or video processing). This change increases the time periods in which memory banks are not accessed by loop operations. The modification allows a memory bank to go into a low-power mode more often and, in addition, allows a more energy-efficient operating mode. The authors of the paper obtained a reduction of memory energy of up to 34%.

	Power Conservation—A Shared Goal for SoC Developers "When it comes to power management in SoC devices, hardware engineers usually determine the power budget. Yet, software controls the use of peripherals and interfaces critical to power management. Power dissipation typically is calculated based on hardware factors such as voltage, frequency and number of gates; software controls the frequency of service, which significantly impacts the power budget. Cadence believes power management responsibility should be shared by both hardware engineers and embedded software engineers. Unfortunately, few tools provide coordinated views of the same problem. The power dissipation challenge underscores the importance of tools that enable designers of complex SoCs to make appropriate choices for hardware architecture, embedded software architecture and physical implementation." Michael O'Reilly Cadence Design Systems

Vendors of hardware/software co-design EDA tools offer products that allow early SoC embedded-software and virtual-hardware integration and evaluation (with varying degrees of success). These tools concentrate on meeting functional and timing specifications—power is not a primary consideration. Design-tool companies need to consider power analysis as part of the domains of both the software and hardware teams of the SoC development project. This paradigm shift will require changes in HW/SW co-development tools that would allow software designers to evaluate their code, when running on a prototype of the target hardware, with respect to power dissipation as well as run time.