Signal Integrity Analysis in Wireless SoCs

The entire electrical signal integrity (ESI) mechanism is very complex. It affects digital operation through IR drop, cross-talk and delay, as well as analog and RF. For the latter, the impact is rather more complicated as very small noise level will produce dramatic influences at any time " and not only in the neighborhood of specific signal transitions as occurs in the digital domain.

1. Wireless systems involve ESI mechanisms.

In summary, noise impacting analog and RF victims is produced by circuits manipulating large electrical signals at high frequencies. These aggressors are any combination of digital, analog or RF functions drawing significant amounts of current on the power supplies which, because of the various physical interconnect and package parasitics involved, result in considerable supply bounce. As illustrated in Figure 1, these parasitics also prevent a perfect collection of all the noise from the aggressors to off-chip, and the remaining noise gets propagated through a combination of substrate, interconnect and package parasitics. Noise injection happens across a wide range of various mechanisms " conductive through substrate biasing contacts, capacitive from source-drain junctions or metal capacitances, as well as well-substrate junctions. The noise disseminating across the whole system is further filtered when transferred through the RC substrate coupled to the RLC parasitics from both interconnect and package.

Amongst all the challenges to address ESI impact on analog and RF victims, modeling noise generation and injection is particularly tricky. The issue is to collect the many power supply and substrate currents in both time and frequency domains. Figure 2illustrates a sample for the simplest possible cell: a CMOS buffer. The contribution here is for one specific set of input slew rate and output load conditions. In real life this has to be conducted over a wide range of operating settings, for all families of each cell in a standard library.

2. These are examples of noise injected by a digital buffer: (a) input and output voltages, (b) supply currents and (c) bulk currents.

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On one side, existing noise models available in popular EDA flows " such as ECSM " tackle only power supply noise in the time domain. On the other side, recent publications considering analog/RF impact focus on substrate noise modeling, and are not compatible with the requirements of commercial software.
In addition, interconnect is not the dominant and only cross-talk medium, unlike in purely digital applications. For analog and RF applications, as depicted in Figure 3, the simulation of noise propagation with various substrate types exhibits the comparable importance of capacitive and inductive coupling through interconnects and package above 1 GHz.

(a)

(b)

3. Simulation shows the results of noise propagated through substrate, interconnect and package with (a) standard CMOS process and (b) very high resistivity substrate.

Moreover, the impact of interfering noise on analog and RF victims is not limited to delay but ranges from poor biasing to full specification degradations " such as the noise figure of LNAs, phase noise and spures on VCOs, etc. " that require noise modeling capabilities both in the time and frequency domains.
To add even greater complexity, of course the respective impact of substrate, interconnect and package parasitics depends on the manufacturing being used, the design style " which in turn relates to the standard cells being used " and system specifications targeted.
At the end of the day, only a dedicated software platform can help to address, effectively, ESI issues to detect system weaknesses early enough in the design flow and to determine the most appropriate solution.

EDA Solution to ESI Analysis
One can summarize the high-level requirements for an EDA solution to ESI as follows:

• Ability to model any silicon and package manufacturing technology,
• Pre-characterization of standard cell library contributions,
• Unified modeling technology to process complex IPs as well as full systems, from early floorplanning to final layout verification,
• Seamless integration into most popular design flows.

4. CWS tools address the problems of ESI in wireless systems.