The EDA industry responded with various ways to augment logic design with low power formats. However, the lack of a single, standard format resulted in costly inefficiencies and an error-prone process resulting form the need to rewrite the low power specification for each tool in the design and verification flow, severely impacting productivity, profit margin, and design quality.

For this reason, Accellera, at the request and assistance of end users and with technical donations and contributions from multiple EDA vendors, developed the Unified Power Format (UPF) to capture low power design intent in a portable and interoperable form that can be used with most design verification and implementation tools throughout the design flow.

Written in tcl, UPF captures the low power design specification for use throughout the RTL to GDSII flow applying consistent semantics for both verification and implementation. Figure 1 shows how a UPF side file augments the HDL code to form a complete design specification at any level of abstraction. Because it is separate from the HDL description and can be read by all of the tools in the flow, the UPF side file is as portable and interoperable as the logic design's HDL code.

1. The UPF side file provides a consistent semantic for all tools throughout the design flow.

Defining System Power States and the Supply Network
When designing the low power aspects of an electronic system, you should start by defining the system power states. For example, a system power state may be such that the modem is in sentinel mode, waiting for an incoming call; the information management system is checking for scheduled appointments; and the rest of the system is in sleep mode to conserve power.

Such a deep sleep state must be defined in terms of the functionality in the system. The UPF provides two commands for defining a power state table, which captures the system power state information.

2. This is an example of a system power state table.

Create_pst defines the name of the table and its columns — the supply nets or ports that are the terms by which a state is defined. Add_pst_state defines the rows of the power state table. The power state table defines the power states in terms of the supply net states, ensuring integration of the system power design with the low power design implementation. The UPF also allows you to specify all the supply network information needed to verify and implement the power supply distribution and control required to realize the system power states.

The supply network consists of the following components and their related UPF commands:

• Power switches created with the create_power_switch command.
• Supply ports, which are defined for power domains (discussed next) and power switches. The create_supply_port command creates a port on a power domain (they are defined for switches in the create_power_switch command).
• Supply nets are created with create_supply_net. Supply nets connect supply ports and logic ports that propagate the supply state (on, off, and voltage value). The connect_supply_net command connects supply nets to one or more ports.
• Supply states. Each supply port has one or more supply state defined. The port may drive only one state at any given time. That state is propagated by the supply net connected to the port. The power state table is defined in terms of these states.

If the design is completely PG (power and ground supply) connected, then no additional work is required. However, the specification of a fully PG connected design is a laborious task. UPF automates the connection of the supply network to the logic elements in the design.

Power Domains
Specifying Power Domains
Power domains enable the automation of supply network connectivity. A power domain is a collection of design logic elements that share a primary supply. A primary supply includes the same power and ground supply nets. This definition of a power domain enables the automatic connection of the primary power and ground nets to all logic elements within the domain.

Power domains are specified with three commands.

• create_power_domain creates the power domain name and may completely or partially specify the logic elements contained in the domain.
• add_domain_elements allows additional logic elements to be added to the domain at a later time.
• set_domain_supply_nets supports IP reuse by separating the implementation specifics of the supply network from the specification of the set of logic elements that must operate at the same voltage level or must be on or off at the same time.

For verification, UPF specifies the semantics of power-off as: primary power and/or primary ground are in the off state. The behavioral semantics of power-down mirrors what happens in actual hardware:

• All registers are corrupted.
• All signals driven by powered-down logic are corrupted.
• All behavioral processes within the powered-down domain are deactivated.

Equally important are the semantics for when power is restored to a domain. On power-up:

• All combinatorial and latch (level sensitive) processes are evaluated, including continuous assignment statements.
• Edge-triggered processes (flops) are not evaluated until the next active edge.
• All behavioral processes are re-enabled for evaluation.

To conserve leakage power, if a block of logic is not used, its power can be gated using power switches. In power gating, a region of logic is partitioned into power domains. Each power domain can have its power independently switched on or off. When power gating a design, it is usually necessary to retain the current value of registers for later restoration on power-up. It is also typically necessary to isolate the signals connecting the powered-down domain to other domains which remain on.

UPF supports the specification of retention and isolation "strategies." In this context, a strategy is a general rule on how to implement these low power design functions. The set_retention and set_isolation commands specify the respective strategies for all registers or logic ports of a power domain or for a defined subset of the registers or ports. To allow IP providers to specify this information, which, as IP providers, they need to know from the details of how that IP is incorporated into a low power design, set_retention_control and set_isolation_control allow the specification of implementation specifics for a corresponding retention or isolation strategy. Specifically, the save and restore signals and their active polarity are specified in the set_retention_control command as the IP integrator is obliged to provide and control these signals. Similarly, the isolation enable signal is specified in the set_isolation_control command.

The set_retention command specifies the retention power and ground supply net and automatically connects it to the retention register's shadow register. Similarly, the set_isolation command specifies the isolation power and ground supply net and automatically connects it to the isolation cell. The same power down and up semantics apply to the behavioral processes implied by the retention and isolation capabilities, relative to the on/off state of the retention and isolation supplies, as applies to design logic elements and the primary power and ground net states.

Although level shifters have the minimal functional semantic of a buffer, low power designs are frequently multi-voltage or employ dynamic voltage and frequency scaling and, thus, require the use of level shifters. A level shifter translates a logic value from an input voltage swing to an output voltage swing. As complex designs utilize multiple voltage domains (power domains operating at different voltage levels), it is necessary to insert level shifters to ensure that a logic '1' in one domain is recognized as a logic '1' in a different domain.

UPF supports the specification of level shifter strategies, including voltage tolerance threshold, whether the strategy applies to up-shift, down-shift, or both. It also supports the designation of which ports a strategy applies to. Implementation tools take this information and, optimizing based on the power state table specification, infer level shifters wherever they are required in the design.

Practical Simulation of Low Power Designs
There are additional key concepts and capabilities of UPF which need to be mentioned, even if briefly.

• Anything created in a UPF specification is created within a specific scope of the logic design. This helps to provide easy mapping from the UPF to the logic design, which facilitates writing the UPF code as well as debugging and analyzing the low power design specification.
• To facilitate verification, UPF defines a support package in SystemVerilog and VHDL. This package defines routines that facilitate querying the current state of a supply net or port and setting the state of a supply port. This allows the testbench to mimic the off-chip power supplies that are connected to the chip's supply pads.
• The ability to define a UPF supply net to an HDL logic value conversion (and vice versa) is provided when a supply net is connected to a logic port in the design. This facilitates integrating the supply network defined in UPF to power-aware models in the design without requiring re-writing of the model to work with the UPF definition and representation of supply net states.