The application guides the MOSFET selection process

In an application such as a load switch in a server power supply, the switching aspects of a MOSFET matter little because the MOSFET is on almost 100% of the time. The on resistance (R_DS(ON)) may be the key figure of merit in such an application. Still other applications, including switching power supplies, use MOSFETs as active switches, and cause the engineer to value other MOSFET performance parameters. Let us consider some applications and their prioritization of MOSFET specifications.

MOSFETs may be best known as switching elements in power supplies, but the components can also offer great benefits at the output of a power supply. Applications such as servers and communications equipment typically employ multiple power supplies in parallel for N+1 redundancy and continuous operation (Figure 1).

Figure 1: MOSFETs used in control of parallel supplies for N+1 redundant topology
(Click on image to enlarge)

The parallel supplies equally share the load and assure the system will continue to operate even if one supply fails. This architecture, however, also requires a way to tie the output of the parallel supplies together while ensuring that a failure in one supply doesn’t affect the other power supplies. A power MOSFET at the output of each supply allows the supplies to share the load and still isolates each supply. MOSFETs used in such a role are called “ORing” FETs because they essentially connect the outputs of multiple supplies in a logical “OR” configuration.

In the ORing FET application, the MOSFET operates as a switch although the switch is almost always in the "on" state, since the power supplies in applications such as servers operate continuously. The switch function only comes into play at startup and shut down, or when a power supply fails.

Designers working on an ORing FET application clearly need to concentrate on different characteristics of the MOSFET than a designer working on a switching-centric application. In the server example, the MOSFET acts as nothing more than a conductor during normal operation. Therefore, minimal conduction losses are the most important concern for designers in an ORing application.

Low R_DS(ON) minimizes BOM and PCB size
Typically, MOSFET manufacturers use the R_DS(ON) parameter to define on-state resistance, and indeed, R_DS(ON) is the most important device characteristic for ORing FET applications. Data sheets define R_DS(ON) relative to both the gate (or drive) voltage VGS and the current through the switch. But given a sufficient gate drive, R_DS(ON) is a relatively static parameter. For example, the Fairchild FDMS7650 data sheet specifies 0.99 mΩ maximum R_DS(ON) with a 10V gate drive.

Low on-state resistance can be doubly important as designers try to develop compact power supplies and minimize costs. Supply designs often require multiple ORing MOSFETS operating in parallel for each supply. Multiple devices can be required to carry the required current to the load. In many cases, designers must parallel MOSFETs to effectively reduce R_DS(ON).

Remember that in DC circuits, the equivalent resistance of parallel resistive loads is lower than the individual resistance values. Two parallel 2Ω resistors equate to a single 1Ω resistor. So in general, a MOSFET with a low R_DS(ON) value, when combined with a high current rating, allows the designer to minimize the number of MOSFETs used in the power supply. (See sidebar at the end, “Minimum R_DS(ON) spec results from IC and package design” for details on minimizing on-state resistance.)

In addition to R_DS(ON), power-supply designers may find several other MOSFET parameters very important in the selection process. In many cases, the designer should closely scrutinize the Safe Operating Area (SOA) curves on the data sheet that describe both drain current and drain-to-source voltage. Essentially, SOA defines the power-supply voltage and current levels at which the MOSFET can be safely deployed.

In the case of an ORing FET application, the chief concern is the current carrying capability of the FET in the fully “on state”. You can actually get that drain current value without going to the SOA curve. Again, using the FDMS7650 as an example, the device is rated at 36A, making it a good fit for typical DC-DC power supplies deployed in server applications.

The SOA curve might come more into play if the design were to implement a hot-swap capability. In the hot-swap case, the MOSFET would need to operate in a partially-on state. The SOA curve defines the current and voltages limits for different pulse times.

Noting the recently mentioned current rating, it’s also worth considering thermal parameters because the always-on MOSFETs are subject to heat. Moreover, escalated junction temperatures can result in a rise in R_DS(ON). MOSFET data sheets specify thermal resistance parameters which, in effect, define how well the MOSFET package conducts heat away from the semiconductor junction. R_θJC, in its simplest definition, is the thermal resistance from the junction to the case.

Expounding on this a bit, in practice the measurement denotes the resistance from the device junction (in a vertical MOSFET this is near the top surface of the die) down to the outside surface of the package, as described in the datasheet.

In the case of PowerQFN packaging, the case is defined as the center of the large drain tab. Therefore, R_θJC defines the thermal effect of the die and package system. R_θJA defines the thermal resistance from the surface of the die to the ambient air, and is specified, typically via a footnote, relative to the design of the PCB including number of layers and the thickness of the copper plating.

Summarizing, the power-electronics design team has no control over R_JC since it is determined by the device packaging technologies employed. State-of-the-art, thermally-enhanced packages, such as Fairchild’s Power 56, yield R_JC specs between 1 and 2 °C/W. Indeed, the FDMS7650 spec is 1.2 °C/W. Design teams can affect R_JA through PCB design. Ultimately a solid thermal design results in more reliability and greater system Mean Time Between Failure (MTBF).

MOSFETs in a switching power supply
Now let’s consider the switching power-supply applications, and how that use demands a different view of the data sheet. By definition, the application requires that the MOSFET regularly switch on and off. While there are dozens of topologies used in switching power supplies, let’s consider a simple example.

The basic buck converter that’s commonly used in DC-DC power supplies relies on two MOSFETs to perform the switching function (Figure 2). These switches act alternately to store energy in an inductor and then release that energy to the load. These days, designers regularly choose frequencies in the hundreds of kHz and even above 1 MHz, because higher frequencies result in smaller and lighter magnetic components.

Figure 2: MOSFET pair used in switching-supply application
(Click on image to enlarge)

Clearly, power-supply design is sufficiently complex, and there is no simple formula for MOSFET evaluation. But let’s consider some key parameters and why those parameters matter. Traditionally, many power supply designers have used a compound figure of merit – gate charge (Q_G) multiplied by R_DS(ON) – in evaluating or ranking MOSFETs.

Gate charge and on resistance are important because both have a direct effect on the efficiency of a power supply. Losses that impact efficiency come primarily in two forms – conduction losses and switching losses.

Gate charge is a primary factor in switching losses. Gate charge is specified in nanocoulombs (nc) and is the energy required to charge and discharge the MOSFET gate. Gate charge and R_DS(ON) are intertwined at the semiconductor design and fabrication process. Generally, devices with lower gate charge specs will have slightly higher R_DS(ON) specs.

MOSFET parameters with secondary importance in switching power supplies include output capacitance, threshold voltage, gate resistance, and avalanche energy.

Some specific topologies also change the relative merit of various MOSFET parameters. For instance, traditional synchronous buck converters compared with resonant converters. Resonant converters minimize switching losses by switching the MOSFETS only when V_DS (Drain to Source Voltage) or I_D (Drain Current) passes through zero. These techniques are referred to as soft switching or ZVS (Zero Voltage Switching) or ZCS (Zero Current Switching). Since switching losses are minimized, R_DS(ON) is more significant in such topologies.

Both types of converters benefit from relatively low output capacitance (C_OSS) values. The resonant circuit in a resonant converter is dictated by the leakage inductance of the transformer combined with C_OSS. Moreover, the resonant circuit must fully discharge C_OSS during the dead time when both MOSFETs are switched off. Therefore, resonant topologies value a low C_OSS. Consider Figure 3, which shows C_OSS plotted relative to V_DS for the Fairchild FDMS7650.

Figure 3: C_OSS plotted relative to V_DS for the Fairchild FDMS7650 MOSFET (Note: C_OSS is the middle curve)
(Click on image to enlarge)

Traditional buck converters, sometimes called hard-switching converters, benefit from a low output capacitance for a different reason. The energy stored at the output capacitance is lost each cycle, whereas that energy is recycled in a resonant converter. So a low output capacitance is especially important in the low-side switch of a synchronous buck regulator.

MOSFETs in motor control applications
Motor control is another application where power MOSFETs find use and where the most important selection criteria might again differ. A motor-control circuit doesn’t switch at the high frequencies found in modern switching power supplies. A typical half-bridge control circuit employs two MOSFETs (a full bridge uses four). But both of the MOSFETs spend a fair amount of time switched off – dead time.

Reverse Recovery Time (t_rr) becomes very important in such applications. When a control circuit switches a MOSFET in a bridge circuit to the off state when controlling an inductive load such as a motor winding, the other switch in the bridge conducts current in the reverse direction temporarily, via the body diode in the MOSFET--hence recirculating the current to continue to supply the motor. When the first MOSFET turns on again, the stored charge in the other MOSFET diode must be removed and discharged through the first, and that is a loss of energy, a short t_rr period minimizes such losses.

So next time your design team needs MOSFETs in a power circuit, think hard about the application at hand before starting the evaluation process. Prioritize the specifications based on what you need rather than based on the particular specifications lauded by the manufacturer.

Sidebar: Minimum R_DS(ON) specification results from silicon and package design

Designers evaluating MOSFET’s can generally learn most of what they need in the selection process by scrutinizing specifications. But sometimes it’s worth a look under the hood at how the IC manufacturer delivered the operational characteristics.

Let’s consider R_DS(ON). You might typically expect that the design of the device and the semiconductor manufacturing process would be solely responsible for the specification. But with R_DS(ON), the package design plays a huge part in delivering a minimum on-state resistance.

Packaging plays a big role in the R_DS(ON) spec because this parameter is focused on conduction loss, and packaging can certainly impact conduction loss. Consider the Fairchild FDMS7650 and the 1-mΩ on resistance described in the main article. About half of the credit for the low R_DS(ON) value is attributable to the package design. The package uses a solid copper clip that connects the source to the lead frame in place of the usual aluminum or gold bond wires. This minimizes the package resistance and lowers source inductance – a major cause of ringing during switching.

About the author
Mike Speed is the Segment Marketing Director for Fairchild Semiconductor. He has over 32 years in the electronics industry. For 22 years, he was involved in system design and development for power supplies. For ten years, he in specialized power analog and power MOSFET advanced technologies. Mike received a Higher National Diploma (HND) in electronics graduating from Chelmer Instititute of Technology, Chelmsford, England.