What really limits MOSFET performance: silicon, package, driver or circuit board? (Part 1 of 2)

Modern low-voltage MOSFETs are now available with on-resistance below 1 mΏ and extraordinary current ratings. Is it really possible or practical to push that much current density through such a small device? Standard one-ounce-copper circuit board is about a half mΩ per square, so how can the package and silicon and interconnect possibly be so low?  Equally important is the switching speed. What limits the practical switching speed?

This article addresses these common questions about today’s high-performance FETs and discusses how to apply them.

In the quest for ever-improved energy efficiency, the incremental improvements in MOSFET silicon and packaging continue unabated. Despite knowing a lot about these devices in last four decades, the challenge of using them effectively in power-supply designs exist even today. Seasoned designers--who have been modeling FET performance for desired applications and keeping that data in a spreadsheet format--have also experienced unsatisfactory results from well-understood models.

Besides the structure and process technology in which the device is fabricated, a MOSFET’s performance is also influenced by several other factors surrounding it. These include:

• package impedance,
• printed circuit board (PCB) layout,
• interconnect parasitics,
• and the switching speed.

In fact, true speed depends on several other factors. For instance, how fast you can switch and still maintain gate control, while fighting the effects of gate-driver loop inductance. Similarly, the low gate threshold aggravates Ldi/dt problems.

Since it is important to understand the transistor’s behavior in a circuit, we will use the half-bridge topology, which is one of the most commonly used in power electronics. In particular, the examples will focus on the synchronous buck converter, a specific implementation of the half-bridge

Common Source Inductance Effects

Figure 1 depicts a half-bridge circuit with parasitics such as stray inductance and resistance contributed by package wirebonds and leadfrane, as well as the board layout and interconnects. The common source inductance (CSI) tends to slow down both turn-on and turn-off of the control FET (high-side FET).

Figure 1: Half-bridge circuit with parasitics
(Click on image to enlarge)

 Being in series with the gate drive, the voltage across CSI adds to the gate drive to keep the FET on, per V = -Ldi/dt, thereby delaying the turn-off of the transistor.  This, in turn, increases the power loss in the control FET, as shown in Figure 2.

Figure 2: Voltage across CSI adds to power loss in the control FET
(Click on image to enlarge)

Higher power losses translate into lower conversion efficiency. Also, with stray inductance, the potential to have voltage spikes in the circuit is high. If these spikes exceed device ratings, it can cause failure. 

To eliminate or minimize this parasitic inductance, the designer must use packages like DirecFET® that has no leads and clips, as well as implement a layout that minimizes interconnect impedance. Unlike standard packages, DirecFET has no wirebonds or leadframe. Hence, it drastically cuts on-resistance, while significantly reducing switch node voltage ringing to curb switching losses.

Mitigating C dv/dt-induced turn-on

Another factor impacting the performance is turn-on induced by C dv/dt (and resulting shoot-through). Undesirably, the C dv/dt induces gate voltage spike on low-side (or sync) FET through the feedback action of the gate-drain capacitance C_GD, causing unwanted turn-on of the low-side FET.

In reality, when a voltage ramp appears across drain-source terminal of Q2, current flows through the total gate resistance R_G via the gate-drain capacitance C_GD as shown in Figure 3(a)_. As a result, it induces a spike in the gate voltage of the sync FET Q2. When this gate voltage exceeds the threshold voltage, it is forced into conduction. Figure 3(b) shows key waveforms of the sync FET Q2 during this mode of operation in a typical synchronous buck converter topology shown in Figure 3(a). 

Figure 3a: Current flows through the total gate resistance via gate-drain capacitance
(Click on image to enlarge)

Figure 3b: Key waveforms of the sync FET
(Click on image to enlarge)

To determine the precise amount of power loss contributed by this phenomenon of the low-side or the sync MOSFET Q2, its drain-source voltage V_{DS_Q2}  is clamped for a period of time. The power loss during this clamp period can be approximated by Equation 1:

Where V_cl  is the value of the clamped V_{DS_Q2}  voltage; f_s is the switching frequency; I_rrm is the peak reverse recovery current; t_cl is the time for the reverse recovery current to reduce from I_rrm  to zero.

It is seen from the above equation that C dv/dt induced loss is a function of Vin, dv/dt and switching frequency, which in turn is driven by driver speed, gate charge Qg, reverse recovery charge Qrr and layout. Hence, to inhibit such an unwanted turn-on means selecting the right sync MOSFET Q2, with small charge ratio (CR) of Q_GD/Q_GS1, where Q_GD is the gate-drain miller charge and Q_GS1 is the gate-source charge before the gate voltage reaches the threshold voltage.

Although lowering C_DS or enlarging C_GS will reduce C dv/dt induced voltage, the C dv/dt induced turn-on at Q2 also depends on the drain-source voltage V_DS-Q2 and threshold voltage V_th. Since gate threshold voltage V_th drops as temperature rises, this problem worsens at higher temperatures. Consequently, low-threshold FETs can be particularly susceptible to C dv/dt problems. 

In reality, to evaluate the sync MOSFET Q2, it makes sense to understand the gate charge behavior of the gate capacitance. Consequently, a clever method of investigating the C dv/dt induced turn-on is to look at the accumulated Miller charge.  To avoid erroneous turn-on of Q2, the designer must ensure that when the drain-source voltage V_DS-Q2 reaches the input voltage, it must be lower than the total charge on the gate-source capacitance.

Part 2 will look at minimizing package parasitics and maximizing performance; it will be posted on August 5, 2010.

About the Author
Eric Persson, Executive Director, Field Applications Engineering at International Rectifier, is a veteran of the power-electronic industry with more than 20 years experience in power electronic design, including inverters, motor drives, AC-DC and DC-DC converters.  He has authored and presented more than 60 tutorials and papers at various international conferences.  In addition he has presented power electronic short courses and lectures for the University of Minnesota, UW Madison, and Purdue University.  Mr. Persson holds 12 US and foreign patents, and is a recipient of the IEEE Third Millennium Medal.