The many facets of power management for computer peripherals

The need for power-interface standardization

The expansion of computer functionality through add-on peripherals requires interface standards in order to realize the full potential of various vendors’ applications. Increasing the functionality of a desktop by adding wireless communication, or increasing the capacity of a laptop computer by adding more memory,  allows a low-cost entry-level computer to be upgraded or tailored to an individual’s needs.

The early 1990s saw the advent of standards for PC add-on cards that allowed external memory from disparate vendors to be added to laptops. The PCMCIA (Personal Computer Memory Card International Association) was formed to standardize the interface, allowing the expansion of laptop memory using a flash or hard disk drive in the form of plug-in add-on cards. Not surprisingly, numerous other vendors quickly realized that their own specialized functions could also be added through PCMCIA cards.

 Manufacturers of storage, communications and gaming applications, to name a few, joined PCMCIA in order to understand the interface or to influence the standards that would allow laptops to use their devices. With the diversity of host systems and card applications, it soon became apparent that the operating- and startup-power requirements of the cards needed careful consideration to prevent power-delivery and system malfunctions.

For example, the disk-drive motor startup or power hold-up capacitors required by many applications were a potential problem. They could cause massive in-rush currents that would overburden the host's power supply, causing system crashes or exceeding the Safe Operating Area (SOA) of the host-delivery MOSFET power switch. Voltages, currents (including surge currents) and sequencing were among the issues addressed by the PCMCIA standards committee. Although the PCMCIA has long been disbanded, its legacy of standardizing power delivery specifications now applies to various other add-ons, including the PC Cards that superseded PCMCIA cards.

System design approach

Like a PC Card, PCI Express (PCIe) addresses power requirements for add-on cards in PCs. The same power-delivery considerations apply and, like PC Cards, PCIe cards can generate secondary voltages that, depending on the application, require sequencing and monitoring. In-rush current precautions must still be taken as peripherals and their associated input capacitance are cycled on and off, inserted and removed.

Power management has evolved from one or two voltages controlled by MOSFET switches which are enabled by discrete logic circuits and ASIC controllers, to ASSPs like Hot Swap/Soft Start Controllers, Supply Sequencers and Trackers, Voltage Supervisors, Reset Generators and Watchdog Timers. However, comprehensive power-management design can become expensive and complex as different applications require different combinations and different versions of ASSPs.

Selecting the right combination of devices can be daunting, with hundreds of devices available from many different vendors. Understandably, designers often simplify their power management designs by ignoring certain possible fault scenarios, or by assuming that certain sequences will always occur.

One example is a power-management design that monitors only the input-supply voltage, and then implements the sequencing of other secondary voltages by tying the "power good" of one regulator to the enable of the next regulator. To be sure, this approach reduces cost and complexity by alleviating the need for a discrete sequencer as well as several precision voltage monitors to monitor each rail. Although this sequential approach reduces cost and complexity, power-supply failure response time can be significantly delayed, resulting in serious data corruption in the form of runt packets and the corruption of stored data.

PCIe voltages, currents and card input capacitance are defined for various slots. Table 1 shows the PCIe specification defining the +12V and +3.3V supplies and tolerances, capacitive loading and maximum current (including in-rush current) for different cards.

Table 1: PCIe power-supply requirements

PCIe also allows for hot-swap cards that require careful attention to limit the startup-voltage slew rate. Voltage supervisors should be used on the inputs to monitor the supplies to determine voltage slew-rate limiting. Although PCIe does not specify sequencing of power supplies, an individual application with secondary supplies can require complex sequencing.

Figure 1 shows the startup sequence of a PCIe card. A key specification shown by the arrow is the 100ms period which occurs after the card is inserted and the 12V and 3V power supplies are stable. After 100ms, the card is enabled by the PCIe bus host by releasing PERST# signal high.

Figure 1: PCIe startup waveforms

Often, the 100ms time is too short a period for the complete sequencing of secondary card supplies and the initialization of large FPGAs, ASICs and other configurable devices. Pulse stretching or delaying of the PERST# signal is often required to meet the individual requirements of each board.  

Figure 2 shows a PCIe card power-down sequence. The PERST# initializes the shutdown, allowing devices to be powered down in a controlled manner before the power supplies decay.

Figure 2: Power-down waveforms

If cards are suddenly extracted while the socket is powered, devices will be powered down abruptly, which can cause catastrophic results. Care should be taken when designing boards so they can handle a surprise extraction and power down the board in a controlled fashion.

Numerous challenges must be addressed when designing PCIe power management. For example:

• In-rush current varies on each design and cannot, even momentarily, exceed the maximum PCIe supply-current specification. Both in-rush current magnitude and duration depend on board input capacitance and various other factors such as the startup currents of FPGAs or ASICs.
• Cards can require a unique hot swap controller circuit for each application.
• Timing may have to be extended beyond the 100ms PERST# signal to slow the reset timing, allowing for power-supply sequencing, FPGA configure time and CPU reset.
• The design should be fast enough to instantaneously respond and power-down the board during a hot-swap extraction without corrupting the system.
• All power supplies should be monitored for both under- and over-voltage conditions to maintain operating integrity.
• The sequencing of power supplies should be flexible, since it can be unique for every application and may need to be changed for design reiterations.
• Boards containing complex chips like CPUs usually require a stable core voltage before initializing the I/O voltages.