(Editor's note: Power Tips is an ongoing series; to see a linked list of all entries from #1 to the latest one, click here.)
In Power Tip #44, we discussed capacitive bypassing requirements for loads with rapidly changing currents. We found it imperative to have low equivalent series inductance (ESL) capacitors physically close to the load, as less than 0.5 nH can create unacceptable voltage excursions.
Realistically achieving this low inductance requires multiple bypass capacitors and multiple interconnect pins into the processor package. Let’s discuss the amount of bypassing capacitance required with realistic di/dt requirements at the power supply output.
Figure 1 shows the power system’s P-SPICE model for this discussion. This figure consists of a power supply with compensation circuitry, modulator (G1) and output capacitor. Included are interconnect inductance and a load model with bypass capacitance, DC load, and stepped loads.
Figure 1: Simple P-SPICE model aids in system design
(click here to enlarge schematic).
First you need to decide whether to treat the power supply and load as separate black boxes, or approach the problem as a complete power system design. If a system level approach, you can take advantage of the load bypass capacitance to reduce the power supply output capacitance, saving system cost. If a black box approach, you can test the supply and load separately. Either way, you need to determine how much bypassing capacitance is needed at the load.
First estimate the interconnect inductance and resistance between the power supply and load. This interconnect impedance (LINTERCONNECT) creates a low-pass filter with the bypass capacitor (CBYPASS). Leverage the assumption that the power supply output impedance is low. Use the characteristic impedance of this low-pass filter (ZO), magnitude of the load step (ISTEP), and allowable voltage variation (dV) to establish bypass filter requirements (Equations 1 and 2):
Solving Equation 2 for Z0, and substituting into Equation 1, gives Equation 3:
Interestingly, the amount of capacitance needed is related to the square of the load current divided by the square of allowable perturbation, which means both should be carefully determined.
Interconnect inductance can range from a few tenths of a nH with a collocated power supply to a few hundred nH's with a remotely located power supply. A good rule of thumb is that the interconnect adds about 15 nH per inch. For a 10 amp load step and a 30 mV allowed perturbation, bypass requirements can range from 500 μF for 5 nH to a ridiculous 50 mF for 500 nH.
This filter also reduces the power supply’s rate of load current rise. If a lossless filter is excited by a square wave of current, the inductor current is sinusoidal. The rate of rise is calculated by differentiating the current waveform in Equation 4 through Equation 7:
With 5 nH of interconnect and 500 μF bypass, a 10-amp step creates a rise rate in the power supply current of 0.2 A/μsec. Larger inductance yields lower di/dt's. These are much lower numbers than system designers usually specify.
In the system approach, minimize total capacitance while maximizing loop bandwidth. Now consider the black-box approach. Here you must make the supply stable with no bypass capacitance and the maximum expected bypass capacitance. As previously stated, interconnect inductance can drive up the load’s bypass capacitance requirement.
This, in turn, impacts capacitance in the power supply using the black-box approach. The range of capacitance connected establishes the power supply’s crossover frequency range. In both voltage and current mode, the relationship is proportional. You maximize the crossover frequency with no load capacitance, but once the load is connected, the crossover frequency falls significantly.
Table 1 presents a comparison of required capacitors for three interconnect inductances for our example system. This data was generated by varying the interconnect inductance, calculating the load bypass capacitance, and designing an appropriate output stage and control loop for the power supply.
Table 1: Keep power system cost down with a system-level approach.
Case 1 has the load and power supply collocated; Case 2 has a medium amount of interconnect inductance between the power supply and load. In Case 3, the system has an extreme amount of inductance characteristic of a cable-connected power supply. The amount of bypass required is directly related to the interconnect inductance.
In this example, Case 3 has 100 times the inductance and, hence, bypass capacitance. This ripples into the power-supply design as the power supply must be stable with and without bypass capacitors. Clearly, the first approach is favored as it uses the minimum amount of capacitors and should cost the least.
In Case 2 of reasonably controlled interconnect inductance, there is a moderate increase in the number of capacitors. A large amount of interconnect inductance as in Case 3, however, creates a significant cost issue. In Cases 2 and 3, there is a convenience factor of stand-alone power supply testing.
Figure 2 compares simulations of the output-voltage variation during load transients with a small and large interconnect inductance. The small inductance response damps out quickly while the large inductance is not as well damped and takes much longer to settle. This is due to higher characteristic impedance and lower resonant frequency.
Additionally, extremely wide and potentially damaging voltage variations can occur, if the load current pulsates at this resonant frequency.
Figure 2: Voltage ringing becomes an issue with large interconnect inductance.
To summarize, high di/dt loads require careful bypassing to preserve power-supply dynamic regulation. Using a low-inductance interconnect is essential between the load and bypass capacitors, as well as between the bypass capacitors and the load. A system level approach leads to the lowest cost solution. Many system engineers overlook this potential cost savings of eliminating power-supply capacitance in favor of conveniently testing the system.
Please join us next month when we will discuss empirical results to determine optimum gate drive timing in a synchronous buck.
For more information about this and other power solutions, visit: www.ti.com/power-ca.
About the author
is a Senior Applications Manager and Distinguished Member of Technical Staff at Texas Instruments. He has more than 30 years of experience in the power electronics business and has designed magnetics for power electronics ranging from sub-watt to sub-megawatt with operating frequencies into the megahertz range. Robert earned a BSEE from Texas A&M University, and a MSEE from Southern Methodist University.
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