Power Tip 46: Time your synchronous-buck FETs properly

(Editor's note: Power Tips is an ongoing series; to see a linked list of all entries from #1 to the latest one, click here.)

   In this Power Tip, we investigate the importance of timing between the high-side and low-side FET gate drives in a synchronous buck regulator. Timing optimization is becoming increasingly important as engineers strive to eke out the best possible efficiency in their power supply.

   There are two transitions during the switching period: the turn-on of the low-side switch, and the turn on of the high–side switch. The low-side turn-on switch is critical because the transition is almost lossless, or a “free ride.” After the high-side switch turns off, the inductor current drives the switch-node voltage losslessly to ground. The best time to turn on the low-side switch is at the end of transition.

   It is not critical if the body diode conducts a short time before the low side turns on, as it does not lead to reverse recovery loss. Any excess carriers in the junction dissipate before the next switching transition.

   However, there is excess conduction loss, if the current remains in the body diode for too long. Timing the high-side FET turn-on is the most important transition. An early turn-on results in shoot-through losses due to cross-conduction with the low-side FET. A late turn-on leads to additional conduction loss and injects excess carriers in the low-side FET body diode, which must be recovered. In either case, efficiency degrades.

   To characterize efficiency as a function of timing between drive signals, I constructed power supplies with adjustable delays on the driver signals. I then evaluated efficiency versus delay times. Figures 1A, 1B, and 1C show the results.

   Figure 1A shows when the high-side FET is turned on before the low-side FET is fully off. An extended Miller region is apparent in the low-side gate drive where the low-side and high-side FETs are both on simultaneously, causing shoot-through current in the power stage. When the low-side FET finally turns off, there is additional voltage overshoot on the switch node.

Figure 1A: Advanced high-side timing creates shoot-through.

(Click here for enlarged image)

   In Figure 1B, the high-side FET is turned on after the low-side FET is off and current has built in the body diode. When the high-side FET is turned on, it recovers the body diode and you would expect a spike of current to ring the switch node voltage. However, that is not evident due to the extremely short reverse recovery times (12 nS) of the MOSFET body diode used. Slower body diodes create significant ringing.

Figure 1B: Body diode conducts with high-side drive delayed.

(Click here for enlarged image)

Figure 1C provides the best power-supply efficiency. The low-side gate voltage drops to near ground before the high-side switch is turned on. The high-side is turned on before the lower body diode conducts, and switch node ringing is minimized.

Figure 1C: Optimum timing improves efficiency and lowers stress.

(Click here for enlarged image)

   Figure 2 presents the efficiency curve for a 12V to 1V/15A, 300 kHz power stage as the gate-drive timing is varied. The left side of the scale represents early turn-on of the high-side switch, (Figure 1A). The right side represents a delayed high-side gate drive (Figure 1B). On the left, there is a drastic fall-off in efficiency due to shoot-through current losses in the power stage. On the right, there is a gradual fall in efficiency.

Figure 2: Driver timing can drastically impact efficiency.

   There are two causes for the gradual fall: conduction loss and reverse recovery loss from the low-side FET body diode. During diode conduction, there is about a 0.7 volt drop across the body diode. During the diode conduction time the maximum possible power supply efficiency is shown in Equation 1 as approximately:

   If the diode conducts for 50 ns out of a 3 μs period, this has about 1.2 percent impact on overall efficiency. With this power stage, the reverse recovery loss is insignificant since MOSFETs with low-reverse recovery times of 12 nS are used.

  To summarize, properly timing of gate-drive signals in a synchronous-buck design is critical for maximizing efficiency. The timing should minimize the low-side FET body-diode conduction time. The high-side FET turn-on is the most critical transition and you should avoid turn-on before the low-side is completely off. This minimizes switching losses while it reduces voltage ringing during transition.

   For a more detailed discussion on this topic, refer to “Predictive Gate Drive Boost Synchronous DC/DC Power Converter Efficiency,” Application Note (SLUA281), Texas Instruments, April 2003.

   Join us next month when we discuss a method for EMI reduction in offline power supplies.

   For more information about this and other power solutions, visit: www.ti.com/power-ca.

Robert Kollman is a Senior Applications Manager and Distinguished Member of Technical Staff at Texas Instruments. He has more than 30 years of experience in the power electronics business and has designed magnetics for power electronics ranging from sub-watt to sub-megawatt with operating frequencies into the megahertz range. Robert earned a BSEE from Texas A&M University, and a MSEE from Southern Methodist University.

Editor's note: Liked this? Want more?

If you are interested in "power" issues such as components; efficiency; thermal concerns; AC/DC and DC/DC supply topologies; batteries; supply ICs; complete supplies; single- and multi-rail management; and supply monitoring: then go to the Power Management Designline home page here for the latest in design, technology, trends, products, and news. Also, sign up for our weekly Power Management Designline Newsletter here.