Reduce THD in digitally-controlled PFCs

Introduction

   Total harmonic distortion (THD) is one of the major criteria in judging the performance of a power factor correction (PFC) controller, and THD requirements have become increasingly stringent. For example, the THD is required to be less than 10 percent at 10 percent load, and in some applications, less than five percent at 20 percent load.

   The factors to affect THD are complex (References 1 through 6). How to meet the THD requirement becomes a challenging task for a PFC design engineer. This article summarizes the most common yet effective methods to reduce the current distortion in a digitally-controlled PFC. All the methods discussed are analyzed and tested.

Dynamic loop compensation

   Unlike other power converters, the input voltage of PFC has a very wide range. It can extend from 80 Vac to as high as 265 Vac. Because of this wide input range, PFC electrical characteristics can vary at different input voltages. A good loop-compensation approach at low line voltage may not work well at high line voltages.

   It is desirable that loop compensation can be dynamically adjusted, based on the input voltage. For example, some devices (such as TI’s UCD30xx family of digital power controllers) provide dedicated hardware to achieve this goal.

   The digital compensator of these types of controllers is a second-order infinite-impulse-response (IIR) filter. The compensator’s coefficients are saved in a set of registers. These register sets are called banks. There are two such banks available and each can store different coefficients.

   At any time, only one bank is active and used for the compensation calculation, while the other bank is inactive. The firmware always can load new coefficients to the inactive bank. During the PFC operation, the active coefficient bank can be swapped at any time to allow the compensator to use different control parameters for a different operation condition.

   With this flexibility, we can store two different coefficient sets. One is optimized for low line and the other is optimized for high line. The coefficients can be dynamically swapped, based on the input voltage. Therefore, the loop bandwidth, phase margin, and gain margin can be optimized at both low line and high line.

Oversampling

   Using a current shunt to sense a boost-inductor current is very common in a PFC design. An operational amplifier (op amp) is used to amplify the current signal to a level suitable for a PFC control circuit.

   However, this current-signal condition circuit does not provide sufficient attenuation to the input current ripple. The current ripple still appears at the amplifier output. Therefore, if this signal is sampled only once in each switching period, there is no perfect fix location where the signal represents the average current all the time. Hence, with single sample, it is very difficult to achieve good THD.

   Digital power controllers like the UCD30xx, for example, can achieve 2×, 4×, 8× oversampling, in addition to the normal single sample per period. An 8× oversampling mechanism is shown in Figure 1.

   With this oversampling capability, the current signal can be sampled and the converted data loaded to the digital compensator eight times during each switching cycle. It effectively averages the current ripple out, such that the measured-current signal gets closer to the average current value.

   Also, the controller becomes less sensitive to noise (signal noise and measurement noise). It has been found that oversampling is one of the most effective ways to reduce current-waveform distortion.

Figure 1: 8× oversampling.

Figure 2. Oversampling test: a) No oversampling, THD=11.14%;

b) With 8× oversampling, THD = 5.18%.

(Click here and here to enlarge)

An oversampling test result on a 360W single-phase PFC is shown in Figure 2. With all the same operation conditions, the THD is reduced from 11.14 percent to 5.18 percent, just by enabling 8X oversampling.

Current distortion reduction at DCM mode

   In discontinuous conduction mode (DCM), when the MOSFET is turned off, the boost inductor current starts to decrease. The current will not stop decreasing when it reaches zero. Rather, it will continue going to negative value and an oscillation between the inductor and the total parasitic capacitance at the switching node occurs, as shown in Figure 3.

Figure 3: Current oscillation in DCM.

(Ch1: switch node voltage, Ch2: PWM, Ch4: inductor current)

(Click here to enlarge)

   The oscillation period and amplitude are dependent on the inductance and capacitance values as well as the operating point. This oscillation results in a significant current distortion and seriously deteriorates the THD (Reference 2).

A new control method developed by TI can force the MOSFET to turn on at the point when the first time the oscillating current rising back from negative value to zero, as shown in Figure 4. Since the MOSFET always turns on at the same zero-current position, the issue described in Reference 2 is solved, and the current distortion is greatly reduced. Also, because of zero voltage switching (ZVS) and zero current switching (ZCS), the efficiency is also improved.

Figure 4: A new ZVS/ZCS control algorithm.

Figure 5. ZVS/ZCS control test result:

a) No ZVS/ZCS control, THD=10.35%;

b) With ZVS/ZCS control, THD=4.76%

(Click here and here to enlarge)

   Figure 5 is a comparison test with and without this new ZVS/ZCS control algorithm on a 360W single-phase PFC. With all the same operation conditions, the THD is reduced from 10.35 percent to 4.76 percent by applying this new control algorithm.

Adding current reference offset

   As mentioned earlier, in DCM mode the oscillating inductor current can become negative, but the negative current will not show up at the output of the current amplifier. Therefore, the amplifier output does not represent the total inductor current.

   This is illustrated in Figure 6. The dashed line is the real inductor current, but only the positive part (the solid line) gets measured. Therefore, the measured average current is bigger than the real inductor average current. This inaccurate feedback signal causes input current to be flat at the AC voltage zero-crossing area and deteriorates the THD.

Figure 6: Current measurement error due to negative current.

A simple way to deal with this measurement issue is to add a DC offset on its calculated current reference to compensate the current-measurement error. This can be done by just adding a few lines of code in the firmware.   

   The above analysis applies to current-shunt-sensing PFC, as well as CT (current transformer)-sensing PFC. Figure 7 is a test result with this method on a bridgeless PFC with CT current sensing. With the same operating conditions, the THD is reduced from 6.85 percent to 3.03 percent by adding a proper offset on the current reference.

Figure 7: a) adding DC offset on current reference test;

b) with offset, THD = 3.03 percent.

(Click here and here to enlarge)