Reduce THD in digitally-controlled PFCs

   For a PFC with CT current sensing, since only the inductor rising current (when MOSFET is turned on) is measured, the current needs to be sampled at a specific position. An example would be the middle of the PWM pulse, so that this instantaneous current can be translated into an average current by a specified mathematical equation.

   However, due to the gate-driver circuit and power-stage delay, the real inductor current is delayed for a certain time, compared with the related PWM pulse. The actual middle point of the inductor’s rising current is a little bit later than the middle point of the PWM pulse. To compensate for this delay, a sample-trigger offset needs to be added (Figure 8).

Figure 8: Current-signal delay and sample-trigger offset.

Figure 9: No sample trigger offset, THD = 7.85 percent;

b) With sample trigger offset by 512 ns, THD = 5.86 percent.

(Click here and here to enlarge)

   Figure 9 is a test result with this sample trigger offset on a 360W bridgeless PFC test board. The test shows that with all the same operation conditions, the THD is reduced from 7.85 percent to 5.86 percent by adding 512 ns sample trigger offset.

Using the maximum measure range of ADC

   A digitally-controlled PFC uses an analog-to-digital converter (ADC) to convert an analog signal into a digital signal. Each ADC has its measurement range. The input signal to the ADC should be between zero and its maximum measurement range. Before connecting to the ADCs, high-voltage analog signals such as V_IN and V_OUT, need to be attenuated to an appropriate magnitude.

   On the other hand, its magnitude should not be attenuated to a very small value. This is because the smaller the signal, the larger the resultant signal-to-noise ratio (SNR). Therefore, the voltage attenuator should be designed to give the maximum ADC output at the maximum input.

   For example, using an ADC with a measurement range from zero to 2.5V to measure an AC input V_IN, and assume the maximum possible V_IN is 290 Vac. The maximum peak value of this V_IN is 410V. The voltage attenuator (usually just a voltage divider) should be designed to give 2.5V at this maximum V_IN, and thus the attenuator’s gain should be 0.0061.

   Similarly, in order to get better measurement for a small signal such as the input current measured across a current shunt, the maximum current (including certain percentage of overhead) needs to be amplified to 2.5V so that it has better SNR.

Using the maximum ADC sample rate

   To regulate the input AC current, the input AC voltage is measured and processed digitally to generate the current reference. Since V_IN is a sinusoidal waveform, it should be measured fast enough to generate an accurate current reference with little delay. An ADC sample rate at the range of 50 kHz should be good enough for a 60 Hz AC signal.

   Usually, the current-loop reference updating rate equals the ADC sample rate. When V_IN is measured, a CPU uses this measured V_IN value, along with voltage loop output, to calculate the current reference. Theoretically, the faster the ADC sample rate, the more accurate is the current reference.

   However, with the clock-speed limitation, the CPU may not have enough time to calculate the current reference at a very-high ADC sample rate. To fully use the high-speed ability of an ADC, the ADC sample rate can be set higher than the current-loop reference updating rate.

   For example, the ADC sampling rate can be set at 100 kHz, while the current loop’s reference is still updated at 50 kHz. A digital IIR filter can be used for these over sampled ADC signals. The benefit of this approach is that the filter can filter out the noise and gives more accurate input-voltage measurement data.

A simple IIR filter example is shown in Equation 1,

Y(n) = X(n) + Y(n) – Y(n)/2                                  Equation 1

Proper maximum duty clamp setting 

   At the AC-voltage zero-crossing area, the PFC PWM duty will get close to 100 percent. However, with CT current sensing, its maximum duty cycle should be limited to less than 100 percent. It should leave enough PFC MOSFET off time for CT to reset.

   Proper maximum-duty clamp setting is important. If the maximum-duty clamp is too high, the CT may not have enough time to reset and become saturated. Once it is saturated, the sensed-current signal becomes smaller and distorted, which could result in deteriorated THD and even circuit failure.

   Conversely, the maximum-duty clamp should not be set very low, either. At the zero-crossing area, the required duty is usually close to 100 percent, and a lower maximum duty means controller cannot provide enough pulse width as required by the control loop; As a result, the current waveform becomes distorted at the zero-crossing area.

Conclusion

   The factors which affect THD are complex. Multiple contributors to the THD may exist at the same time. There is no single panacea for all the problems.

   However, understanding all of these distortion contributors helps a designer to solve the problems one by one and achieve a final goal. This article summarizes the common root causes of PFC current distortion and provides practical solutions to each of them. Test data on a 360W PFC test board validates the solutions and provides a quantitative comparison of THD reduction for the solutions.  

References

1. J. Sun, “On the zero-crossing distortion in single-phase PFC converters,” IEEE Trans. Power Electron., vol. 19, no. 3, pp. 685–692, May 2004.
2. K. De Gusseme, D. M. Van de Sype, A. P. M. Van den Bossche, and J.A. Melkebeek, “Input-Current Distortion of CCM Boost PFC Converters Operated in DCM,” IEEE Trans. on Ind. Electron., vol. 54, no. 2, pp. 858–865, Apr. 2007.
3. P. Todd, UC3854 controlled power factor correction circuit design, Application Note U-134, Unitrode, 2003.
4. J. C. Salmon, “Techniques for minimizing the input current distortion of the current-controlled single-phase boost rectifier,” IEEE Trans. Power Electron., vol. 8, pp. 509–520, July 1993.
5. Y. K. Lo, S. Y. Ou, and H. J. Chiu, “On evaluating the current distortion of the single-phase switch mode rectifiers with current slope maps,” IEEE Trans. Ind. Electron., vol. 49, pp. 1128–1137, Oct. 2002.
6. C. Zhou and M. Jovanovic, “Design trade-offs in continuous current-mode controlled boost power-factor-correction circuits,” Proc. High Frequency Power Conversion, 1992, pp. 209–220.

About the authors

Bosheng Sun is a Systems Engineer at Texas Instruments where he is responsible for system and firmware design, development and testing for TI’s Fusion Digital Power products. Bosheng received his MSEE from Cleveland State University, Ohio.

Zhong Ye is a Systems Engineering Manager for High-Performance Isolated Products at TI. Zhong received the MSEE from Fuzhou University in and a Ph.D. degree in Power Electronics from Toledo University.

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