Power Tip 49: Avoid these common multi-layer ceramic capacitor pitfalls

(Editor's note: Power Tips is an ongoing series; to see a linked list of entries, click here.)

Please join us next month when we will continue to discuss capacitor selection in switched-mode power supplies. The following is part 1:

Multi-layer ceramic (MLC) capacitors have become extremely popular in power electronics due to their small size, low equivalent series resistance (ESR), low cost, high reliability, and high ripple current capacity. Commonly, they are used in lieu of electrolytic capacitor to enhance system performance.

MLC capacitors have the advantage of a high relative permittivity material (2000-3000) compared to electrolytics with relative permittivity of 10 with the aluminum-oxide insulation of an electrolytic capacitor. The difference is important because capacitance is directly related to permittivity. On the positive side for the electrolytics, the aluminum-oxide thickness that sets the plate separation is much less than the ceramics that can result in higher capacitance density.

The permittivity of the ceramic capacitor is not stable over temperature and DC bias and needs to be understood in the design process. High permittivity ceramics are classified as Class 2. Figure 1 shows how they are grouped with a three-digit description, such as Z5U, X5R and X7R. For instance, a Z5U capacitor has a temperature rating of +10 to +85^o C with a variation of +22/–56%. Even the more stable dielectrics have a sizable capacitance variation with temperature.



Figure 1: Class 2 dielectrics are grouped with a three-digit classification. Watch that tolerance!

Things get much worse when you examine the capacitance dependence on applied bias. Figure 2 presents the bias dependence of a 22 uF, 6.3 volt, X5S capacitor that you typically would use as the output capacitor in a 3.3 volt point-of-load (POL) regulator. The capacitance drops 25 percent at 3.3 volts, resulting in increased output ripple and a significant impact on control loop bandwidth. If you tried to use this capacitor at 5 volts out, between temperature and bias, the capacitance could drop as much as 60 percent and might result in an unstable power supply due to a 2:1 increase in loop bandwidth. This is a point that ceramic capacitor vendors gloss over.


Click on image to enlarge.

Figure 2: Watch out for the decrease in capacitance with applied bias.

The second potential pitfall with ceramic capacitors is that they have a relatively small amount of capacitance and a low ESR. This can create problems in both the frequency and time domain. If they are used as input filter capacitors on a power supply, they can easily resonant with the input interconnect inductance and create an oscillator as we discussed in Power Tips 3 and 4. To see if you have a potential problem, estimate the parasitic interconnect inductance as 15 nH per inch and compare the filter output impedance to the power supply input resistance per the articles. A second potential problem exists in the time domain and can be experienced in systems like power-over-Ethernet (POE).

In these systems, the power source is connected to a load through a large interconnect inductance. The load is switched on through a switch and may be bypassed with ceramic capacitors. The bypass capacitors and interconnect inductance can create a high Q resonant circuit. Closing the switch at the load can create an over-voltage condition as the load voltage can ring to twice the source voltage. This can lead to unexpected circuit failures. For instance, in the POE, the voltage ratings on the load components can migrate as much as double the source voltage ratings.

A third potential pitfall lies in the fact that the ceramic capacitors are piezoelectric. That is, when the voltage changes on the capacitor, its physical size changes, which can result in an audible noise. Examples of problem applications are when the capacitors are used as output filter capacitors where a large load transient current is present or in “green” power supplies that go into burst modes at light-load conditions. Workarounds to this issue include:

• changing to a lower permittivity ceramic material like COG
• using a different dielectric such as film
• using leaded versus surface mount technology (SMT) components which are tightly coupled to the printed wiring board (PWB)
• using a smaller footprint device to reduce stress coupled into the board
• using a thicker part to reduce applied voltage stress and physical distortion

Another issue with SMT ceramic capacitors is that their solder joints are prone to cracking if the PWB flexes, and due to thermal coefficient of expansion (TCE) mismatch between them and the PWB. There are a number of precautions you can take to mitigate this issue:

• restrict package size to 1210.
• keep capacitors away from high flexure areas such as corners
• orient capacitors in the short direction of the board
• keep board mounting points away from corners and edges
• be mindful of potential board flexing during all assembly steps

To summarize, multilayer ceramic capacitors can provide cost savings, reliability and life improvements, and size reductions over electrolytic capacitors – if you are mindful of their pitfalls. They can have very wide capacitance tolerances, so you need to evaluate their performance over temperature and bias voltage. They are piezoelectric, meaning they can generate audible noise in systems with pulsating currents. Finally, they are prone to cracking so steps to mitigate the issue are required. All these issues can be worked around. Hence, the MLC capacitor is continuing to become very popular.

For more information about this and other power solutions, visit: www.ti.com/power.

Robert Kollman is a Senior Applications Manager and Distinguished Member of Technical Staff at Texas Instruments. Kollman earned a BSEE from Texas A&M University, and a MSEE from Southern Methodist University.