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docdivakar
Kris, this is about a decade-old technology developed by TI (was using 15micron ...
Clif Tsai
Hope the wafer-packaging foundry collaboration will be smart enough to create a ...
UMC copper process targets power management ICs
Peter Clarke
1/16/2013 7:52 AM EST
LONDON – Foundry United Microelectronics Corp. (UMC) has introduced a thick plated copper manufacturing process for use with power management ICs (PMICs).
The thick-plated copper process was developed in collaboration with Chipbond Technology Corp. (Hsinchu, Taiwan) and provides thick copper layers to achieve higher current flows and improved thermal conductivity. Used as a top layer the thick copper reduces chip resistance by 20 percent or more compared with conventional aluminum top metal.
This can be used in designs to increase power conversion efficiency and thereby extend battery life, said UMC (Hsinchu, Taiwan). The use of PMICs with integrated voltage conversion is expected to reduce component count and be in demand for use in smartphones, tablet computers and thin computers, UMC added.
The thick plated copper process is available for use with BCD (bipolar, CMOS, DMOS) processes at 0.35-, 0.25- and 0.8-micron nodes manufactured on 200-mm diameter wafers. UMC said a 110-nm BCD process with thick plated copper would be available in the next few months. UMC said it can provide design rules and qualification reports.
UMC did not state whether the use of thick copper plating is restricted to replacing or augmenting the top layer metal in IC production.
"Working with Chipbond, we are pleased to offer UMC customers an integrated service for a TPC process to address these requirements at chip-level to enhance end-product performance while reducing size. We look forward to the rapid adoption of this solution as we roll-out our TPC process for a variety of UMC technologies," said Anchor Chen, senior director of the specialty technology development division at UMC, in a statement.
Related links and articles:
www.umc.com
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iniewski
1/16/2013 10:37 AM EST
20% lower resistance doesn't sound like much...I am surprised that would developed a special process option for this...why not use it across the board?
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docdivakar
2/21/2013 5:55 PM EST
Kris, this is about a decade-old technology developed by TI (was using 15micron Cu back then) and was used in its Swift group of Power Management products. The TPS54672 (with integrated MOSFETs) used a 0.8um BiCMOS process in a TSSOP PowerPAD package and the die used thick Cu in an RDL process which was done typically in a backend fab in those days. I believe the process technology was developed by Unitive with TI's active participation (Unitive has since been a part of Amkor).
Since the Swift product days, the backend metallization for thick Cu has further improved. The article doesn't mention about patent claims TI had that prevented a number of other PMIC companies from using this technology.
MP Divakar
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peter.clarke
1/16/2013 1:45 PM EST
Well copper is highly contaminating in a fab, so I suspect that UMC/Chipbond are plating copper on to a die as final metal layer step, possibly out of the fab.
So then the question is one of desiging PMICs for greater current and thermal performance and which conventional BCD processes you apply the thick-copper plating.
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Kresearch
1/16/2013 3:56 PM EST
It is just a marketing tactic to combine UMC(wafer Foundry) and Chipbond(Bumping house) services. Solution would be like typical RDL process. Anything new? It seems not.
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Clif Tsai
1/17/2013 3:50 PM EST
Hope the wafer-packaging foundry collaboration will be smart enough to create a robust interconnect system using Cu wire/bump to resolve some of the Cu-based interconnect issues in assembly process and reliability.
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