Programmable Logic Design Features

Reproducing a Cray 1 supercomputer in a single FPGA

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LED improvements extend automotive applications

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Is there a future for hybrid vehicles? Part 1

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Using requirements planning in embedded systems design: Part 4 - Defining the system-level design

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Fob functionality goes beyond the car

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Audio amplifier power supply design - Part 2: External supplies, inrush current & RF emissions

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Reusability, usability and flexibility

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Using switched capacitors to create programmable analog logic blocks in mixed-signal designs

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Enhancing robust SEU mitigation with 28-nm FPGAs

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Providing battery-free, FPGA-based RAID cache solutions

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Technical Papers

Extending Transceiver Leadership at 28 nm

Extending the Spartan-6 FPGA Connectivity TRD to Support the Aurora 8B/10B Serial Protocol

Actel SmartFusion: Intelligent, Innovative Integration

Increasing Design Functionality with Partial and Dynamic Reconfiguration in 28-nm FPGAs

Using FPGA Prototyping Board as an SoC Verification and Integration Platform

Enabling High-Precision DSP Applications with the FPGA Industry's First Variable-Precision Architecture

Leveraging FPGA in PCB System Designs

Spartan-6 FPGA Connectivity Targeted Reference Design Performance

FPGA Design Methods for Fast Turn Around

Building an IP Surveillance Camera System with a Low-Cost FPGA

Courses and Webinars

Linaro 10.11 release and beyond

How to Verify the Data in Your LTE Downlink Signal

Conquering the Memory Bandwidth Bottleneck On-Chip

Theories, Techniques, and Validation of Over-The-Air (OTA) Test Methods for Evaluating the Performance of MIMO Handsets

Debugging High Speed Memory and Serial buses with Greater System Visibility

SSL Drivers Reliability – Dispelling the Myth on Poor Driver Reliability

Tips for Embedding Flexible Analog Interface IP into Digital SoCs for Broadband Communications

Addressing Software Challenges on Multi-core and Multi-chip Platforms

Fundamentals of Power-Supply Distribution Topologies

Industry's First - 36-V LDO

Teardowns

Micron drives process integration with 42-nm DDR3 SDRAM

Teardown: Inside the art of pulse oximetry

Ear bud headphones jam lots of complexity in a tiny package

Eye-Fi uses Secure Digital (SD) card slot for Wi-Fi in cameras

Teardown: Inside Cisco's Flip UltraHD digital camcorder

UPDATE: B'com, Toshiba win sockets in iPhone 3GS

Comparing the AX508 to the AX502

A first look inside the Palm Pre

What you need to know about Microsoft's BlueTrack mouse

NAND Flash - The New Era of 4 bit per cell and Beyond

More Design Teardowns >

Reference Designs

Quantenna debuts 802.11n 4x4 MIMO wireless video bridge ref design

Quantenna Communications Inc. has debuted a complete reference design based on its QHS600 IEEE 802.11n wireless LAN (WLAN) 4x4 multiple input, multiple output (MIMO) chipset.
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Lattice adds over 90 reference designs for PLDs

Lattice Semiconductor Corp. has released more than 90 reference designs optimized for the MachXO and ispMACH 4000ZE PLDs.
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Commentary

Are FPGA tools dumb?

Brian Bailey

In a recent discussion about the necessary differences between tools for ASIC developers as compared to the needs of FPGA users, one expert called it 'a dumbing down,' but guest blogger Brian Bailey says 'that is just wrong.'

Join  post comment   1 comment    last comment  Max the Magnificent
At the moment I think some of the more interesting EDA tools are appearing in the FPGA arena, ...

Book Review: The Disappearing Spoon by Sam Kean

Clive Maxfield

This little scamp is jam-packed with interesting nuggets of knowledge and tidbits of trivia about the periodic table and the elements it represents – it's way more interesting than I would ever have imagined.

Join  post comment   4 comments    last comment  kapow
Yes I am in the midst of this book right now. Very interesting read! I would also recommend ...

In-vehicle Internet grows slow and steady

Rick DeMeis

The popularity of smart phone apps is driving demand for in-vehicle Internet connectivity.

Join  post comment   6 comments    last comment  Silicon_Smith
I feel the idea is a little exaggerated in its application and usefulness. If the driver of a ...

Man pays bill with drawing of spider

Clive Maxfield

I just discovered a really interesting website; the first story to tickle my fancy was about an Internet prankster who attempted to pay a bill with a drawing of a spider.

Join  post comment   2 comments    last comment  ReneCardenas
Thanks for pointing our way to another time balck hole, and let me spare some idle time. Lot of ...

Avnet and Actel offer great SmartFusion mixed-signal FPGA workshops

Clive Maxfield

Avnet Memec and Actel are hosting a series of one-day workshop that provide hands-on experience working with Actel's SmartFusion mixed-signal FPGAs and design tools.

Join  post comment   6 comments    last comment  SkiFaster
The Avnet Speedways were specific to North America, although they also ran events in Europe earlier ...

FPGA-to-ASIC conversion with zero NRE

Clive Maxfield

KaiSemi performs automated FPGA-to-ASIC conversion with Zero NRE, functional guarantee, and a very short cycle time; this is a full turnkey solution that is seamless to the customer.

Join  post comment   4 comments    last comment  Max the Magnificent
Hi there -- re your questions -- I don't know the answers yet -- but keep the questions coming and ...

How strong are your IP assets?

Thomas Marlow

There is no question that a portfolio of patents can provide tremendous value to a company. In fact, many will agree that trying to compete in a high technology industry without adequate patent protection is insane if not merely futile.

Join  post comment   10 comments    last comment  tmarlow
You are absolutely correct. This is indeed a first step in a large process (resources permitting). ...

More about mediocrity

Jack Crenshaw

Jack Crenshaw continues his discussion about strategies to employ to improve software quality and whether or not quality software come from quality people, or can you get quality software from mediocre people?

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Mediocrity starts at the top with a set of expectations and priorities. Expediting (in balance) has ...

More on requirements: a few simple rules

Jack Ganssle

What makes great requirements? A few simple rules serve as guidance

Join  post comment   7 comments    last comment  VK3DGN
Requirements should also be consistent with each other, and standalone. I believe that specifying ...

Embedded processors in FPGAs amplify verification challenges

Dave Orecchio

In an entry on the RocketBlog, Dave Orecchio of Gate Rocket says embedded processor cores for DSP, microcontroller and microprocessor functions are becoming increasingly common in FPGAs.

Join  post comment   1 comment    last comment  Dr DSP
I guess a related question is what level of simulation is required for an embedded FPGA. Since it is ...

Recent Comments

chanj  09.07.2010
Apple to take bite out of Moto
I am glad to see the comeback of Moto. Droid X is indeed a good phone. There are a couple of other ...
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chanj  09.07.2010
Power Integrity Issues in System Design
Signal integrity is indeed a common problem happening in a new system. I had similar experience that ...
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Dexton  09.07.2010
FLIRTing with 8-bit MCU OSes
Hi Dave, Site http://www.friendlylittletasker.org is down. :( Regards, John
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Most Commented

Enter the EE Life August 2010 Cartoon Caption Contest

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Apple should build a fab

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Why China should bar Cisco, Moto and HP

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Opinion: Microsoft dying? Don't bet on it

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Mandating an FM radio in every cell phone: what are they thinking, and why?

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