Intel's new CEO shakes things up
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Improving power consumption in NFC and HF RFID card detection systems
Prepare yourself for Geek Pride Day (May 25)
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World's first field-programmable radio frequency (FPRF) chip
Imperas launches multicore software development tools
All eyes on Zynq SoC for smarter vision
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Artificial heart ready for human trial
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Altera to buy Enpirion for on-chip power conversion
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Moving to SystemC TLM for design and verification of digital hardware
Multicore debug goes heterogeneous at PMC-Sierra
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The Programmable Logic Designline is edited by Clive (Max) Maxfield. Here in programmable logic space (where no one can hear you scream) we are interested in anything and everything to do with programmable logic, including FPGAs, CPLDs, CSSPs, PSoCs... along with their associated design and verification tools and flows... Please contact