Virtually every ASIC ends up an FPGA

Over the past decade, designers around the world have argued over the relative merits of using ASICs or FPGAs to implement digital electronic designs. This ongoing discussion has typically positioned the performance advantages and low power consumption of fully customized ICs against the flexibility and low NRE costs of FPGAs. Should a design team make the formidable up-front NRE investment in an ASIC design in order to maximize performance, reduce footprint and drive down costs at high volumes? Or is the design team building an end product for a market that demands the highly configurable feature sets and quick turnaround that only FPGAs can provide?

Surprisingly, the escalating challenges of high-density IC design are, in many ways, making that argument irrelevant. As ASIC designers migrate to each new process node, designs grow more complex, software content increases and verification runtimes lengthen. Moreover, recent research indicates that over 60 percent of respun ASICs fail not because of issues with timing or power, but because of logical or functional errors. For this reason, functional verification has become the single most critical phase of the ASIC development cycle, and often the most time-consuming. An increasing number of ASIC designers find that they can best meet their requirements by prototyping the functional equivalents of their designs as FPGAs. In fact, more than 90 percent of all ASICs today are either partially or completely prototyped as FPGAs before tape-out. Thus the question is no longer whether to implement an IC design as an ASIC, or as an FPGA. To meet the demands of today's markets, most design teams must do both.

Verification options
Given the critical need for first-pass silicon and the escalating possibilities for bugs as ASIC densities climb and design complexities increase, designers clearly need a verification methodology that can not only find all bugs in complex chip designs but also do so in reasonably short times. Traditional software simulation techniques can no longer support design teams who are racing to squeeze into tight time-to-market windows. Take a typical mobile phone chipset design. Although RTL simulation offers a high level of visibility into the design, the low performance associated with software simulation means that booting the phone chipset could take as long as 30 days, making it unfeasible and, therefore, significantly limiting the level, and amount, of verification possible. Hardware/software co-simulation approaches that use higher-level models can reduce the time required for this sort of OS boot to 10 days, but even that is still not very useful. Moreover, these approaches still require the development of complex testbenches, which, by their very nature, are always incomplete. A "C" model simulation offers shorter runtimes, perhaps even of only 24 hours, but it can't deliver the level of detail typically required by ASIC designers.

What ASIC designers need is a verification strategy that offers speeds approaching that of the ASIC. They need a methodology to leverage real-world stimulus, not a testbench. They need a verification methodology that is highly affordable and easily deployable in order to support distribution for hardware and software debug within the whole design team. Furthermore, they need a verification strategy able not only to run operating system and application software at speed but also to easily integrate external system components and interfaces.

Already today, more than 90 percent of all ASICs and ASSPs are either partially or completely prototyped in FPGAs, making FPGAs a pivotal IC verification methodology.

By implementing an ASIC prototype as an FPGA, designers can run millions of test vectors per second, a process roughly one million times speedier than traditional software simulation. A mobile phone's chipset, which might spend up to a month in a software simulator, runs in as little as 30 seconds as an FPGA prototype. That performance advantage offers enormous benefits during the software and system integration stages of the design cycle. By running at speeds approaching the ASIC itself, an FPGA prototype allows designers to verify embedded or application software against their hardware, stream video or networking data to test performance and identify hard-to-find bugs and, if the design incorporates embedded CPUs, verify an operating system's performance before the ASIC design is complete. Moreover, by applying real-world stimulus to the design, verification engineers can eliminate the time-consuming task of testbench development.

Requirements of an ASIC-to-FPGA conversion tool
Perhaps the bigger question for ASIC designers is not whether to prototype their designs in FPGAs but, rather, what types of capabilities they should look for in an ASIC-to-FPGA conversion tool. Few designers have the time or resources to implement their IC as both an ASIC and an FPGA. Distinct differences separate not only the technologies themselves but also their use. Thus, for any ASIC prototype platform to succeed, it must first of all be able to accurately translate the architectural distinctions separating ASICs and FPGAs. Common ASIC features, such as gate-level components or gated clock tree structures, are too difficult and time-consuming to convert manually. Moreover, significant differences distinguish ASIC and FPGA memories. Ideally, an ASIC-to-FPGA conversion tool will automatically recognize those design elements and map them into FPGA-equivalent features. As part of that process, it will also perform such tasks as gated clock conversions and signal-to-trace assignments.

Partitioning is a second necessary function of an ASIC-to-FPGA tool. As ASICs have grown increasingly complex, integrating a wider array of functions, designers seeking to verify their designs rapidly and cost-effectively have had to partition their chips' functionalities across several FPGAs. Many ASIC designers opt to perform this task by hand an error-prone and inherently risky process. Most ASIC designers do not build their designs expecting to later partition them across multiple FPGAs as part of verification. Accordingly, the partitioning process can be highly complex and time-consuming. Does the ASIC prototyping tool automatically partition the RTL across multiple FPGAs? Can it perform this task without requiring changes to the RTL source code?

Using FPGA-based ASIC prototypes lets designers run verification many million of times faster than traditional software simulation-- a mobile phone design that previously took a month to boot up in a software simulator now can run in as little as 30 seconds.

In some cases, when a designer is highly familiar with the original ASIC design or wants to focus on the verification of certain functions, it may be advantageous to perform some of the partitioning task by hand. Does the ASIC prototyping tool allow the user to automate part of the partitioning process while performing other parts manually? Furthermore, in many designs, pin limitations pose a major challenge. Does the ASIC prototyping tool support I/O multiplexing technology, allowing users to share pins, thus circumventing this common limitation?

The ability to view the states of signals internal to the FPGAs on the board is also crucial in the verification process, but inserting logic to enable debug access is a tedious and lengthy task. Any ASIC prototyping tool under evaluation should support multiple mechanisms for performing this job. Closely inspect the debug-insertion technologies the tool supports and note how easily they allow users to observe signals while debugging.

Verification engineers must also ask how the ASIC prototyping tool allows users to measure and tweak performance once the design is ready for synthesis. Does the tool allow users to optimize timing paths? Does that ability extend to those paths crossing multiple FPGAs? Does the tool provide any reports or analysis on timing performance that users can evaluate with the prototype before the actual programming of the hardware?

By using programmable logic as a prototyping platform to gain insight into and verify an ASIC's functionality, designers can quickly and affordably identify potential bugs, reducing the overall risk associated with products while meeting time-to-market deadlines.

Juergen Jaeger is Senior Director, ASIC Verification Marketing, at Synplicity, Inc. He has over 20 years' experience in marketing verification solutions for ASICs and FPGAs. He studied electrical engineering at the Fachhochschule of Kaiserlautern, Germany, as well as computer science at the University of Hagen, Germany.