How to combine FPGAs and DSPs to get the best base station performance

Suppliers of DSP chips and programmable logic may differ over which device type is best for new wireless system designs but the design strategies their customers are actually implementing is what's most important.

And today, designers are mixing PLDs and DSPs. "Intelligent partitioning" between these two device types gives wireless systems the best combination of features and cost-effectiveness.

Besides the obvious goals of meeting specifications, the practice of mixing DSPs and FPGAs brings a measure of future proofing as well as potential for risk-free cost reduction. This article expands on these design strategies and provides examples of FPGA+DSP system partitioning for wireless basestations that illustrate why combining programmable logic with DSP can assist designers with their projects.

Growing bandwidth requirements
Market needs for higher data rates are driving the evolution of wireless cellular systems from narrowband 2G GSM, IS-95 systems to current-generation W-CDMA-based 3G and 3.5G systems supporting peak data rates up to 10 Mbps.

For future 3GPP long-term evolution specifications, complex signal processing techniques such as multiple-input multiple-output (MIMO) along with new radio technologies like orthogonal frequency-division multiple access (OFDMA) and multicarrier Code Division Multiple Access (MC-CDMA) are considered key to achieving target throughputs in excess of 100 Mbps.

Alternate OFDM-based broadband wireless systems such as WiMAX have similarly evolved, achieving transmission speeds in excess of 70 Mbps. The improvement in data rates has been possible primarily through the use of higher order modulation techniques and variable rate channel coding.

Complex spatial signal processing schemes such as beamforming and MIMO antenna techniques are also proven technologies for increasing data rates at the expense of additional hardware. These enabling technologies pose significant challenges for OEMs needing to design basestations that are not only scalable and cost-effective but also flexible and re-usable across multiple evolving standards.

Basestation design requirements
Wireless systems designers need to meet a number of critical requirements including processing speed, flexibility, and time-to-market. These stringent requirements ultimately drive the hardware platform choice. Some of the major challenges include:

• Processing bandwidth: WiMAX broadband wireless systems have significantly higher throughput and data rate requirements than W-CDMA and cdma2000 cellular systems. To support these high data rates, the underlying hardware platform must have significant processing bandwidth. Additionally, several advanced signal processing techniques such as Turbo coding/decoding and front-end functions including fast Fourier transform/inverse fast Fourier transform (FFT/IFFT), beamforming, MIMO, crest factor reduction (CFR), and digital predistortion (DPD) are computationally intensive and require several billion multiply and accumulate (MAC) operations per second.
• Flexibility: WiMAX is a relatively new market and is currently in the initial development and deployment stages. Similarly 3GPP LTE is being defined and will go through numerous revisions before being finalized. It is still unclear which of the many "mobile broadband technologies" (i.e. WiMAX, Wibrow, Super 3G, LTE, Ultra 3G, etc.) will be embraced by the marketplace. Under this current scenario, having flexibility and re-programmability in the end product is necessary to provide a standards-agnostic or multi-protocol basestation. Systems offering this flexibility can significantly reduce the CAPEX and OPEX costs for wireless infrastructure OEMs and operators while alleviating risks posed by constantly evolving standards.
• Cost-reduction path: A valuable lesson learned from designing and deploying 3G systems is the importance of establishing a long-term cost-reduction strategy in the beginning. Evolving WiMAX and LTE standards are expected to stabilize. This will likely lead to a situation where cost of the final product will be more important than flexibility for OEMs and service providers to remain competitive in the marketplace. Choosing the right hardware platform for prototyping that provides a seamless cost-reduction path for production volumes will save millions of dollars in engineering costs that would otherwise be required for system re-design.

System architecture design and logic task partitioning
Signal-processing data path and control operations make up the bulk of the processing load in a wireless basestation. Most architectures implement the system control, configuration, and the signal-processing data path using a combination of microcontrollers (MCUs), FPGAs and programmable DSPs.

The MCU controls the system, while the FPGA and DSP handle the data-flow processing. Systems with light processing demands and control-oriented tasks are implemented in software on a DSP; heavier loads are best implemented in FPGAs that provide significant parallel processing benefits. The combination of DSPs and FPGAs ensures complete system flexibility and offers reprogrammability to fix bugs or even support entirely different standards.

The exact partitioning between FPGAs and DSPs depends on processing requirements; system bandwidth as well as system configuration; and the number of transmit and receive antennas. Figure 1 shows a typical DSP/FPGA partitioning for baseband physical layer (PHY) functions in an OFDMA-based system such as WiMAX or LTE.

Click here for Figure 1
Figure 1: DSP/FPGA partitioning for OFDMA systems.

By incorporating advanced multiple antenna technologies, the throughput offered by such systems is expected to be between 75-100Mps. The baseband PHY functionality can be broadly categorized into bit-level processing and symbol-level processing functions. Following is an overview of these functions and how FPGAs are used to complement DSPs for implementing both bit-level and symbol-level functions.

Bit-level processing
The bit-level blocks include randomization, forward error correction (FEC), interleaving, and mapping to quadrature phase shift keying (QPSK) and quadrature amplitude modulation (QAM) functions on the transmit side. The corresponding receive processing bit-level blocks are symbol de-mapping, de-interleaving, FEC decoding, and de-randomization. All bit-level functions except FEC decoding are relatively straightforward and not computationally intensive.

For example, randomization involves modulo-2 addition of the data bits with the output of a simple pseudo-random binary sequence generator. Although FPGAs offer more flexibility for bit-level manipulations than DSPs with fixed bus widths, the low computational complexity allows such functions to be easily implemented on DSPs.

Conversely, FEC decoding—including Viterbi decoding, Turbo convolutional decoding, Turbo product decoding, and LDPC decoding—are computationally intensive and consume significant bandwidth when implemented on DSPs. FPGAs are widely used to offload these functions and free up bandwidth on DSPs to perform other functions.

The same FPGA can also be used to interface to the MAC layer as well as implement certain lower MAC functions such as encryption/decryption and authentication. Altera’s low-cost Cyclone II FPGAs are well suited to implement such DSP co-processing functionality.